AndreiGrozav 10c99562cf axi_logic_analyzer: Add extra reg pipe to avoid latch		2019-10-28 13:13:10 +00:00
..
Makefile	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
axi_logic_analyzer.v	axi_logic_analyzer: Add extra reg pipe to avoid latch	2019-10-28 13:13:10 +00:00
axi_logic_analyzer_constr.xdc	constraints: up_xfer_cntrl and up_xfer_status have its own constraints	2018-04-11 15:09:54 +03:00
axi_logic_analyzer_ip.tcl	library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl	2019-06-29 06:53:51 +03:00
axi_logic_analyzer_reg.v	axi_logic_analyzer: Add module cascade support	2019-08-22 18:06:10 +03:00
axi_logic_analyzer_trigger.v	axi_logic_analyzer: Add extra reg pipe to avoid latch	2019-10-28 13:13:10 +00:00