pluto_hdl_adi/projects/common
Laszlo Nagy fe2b43ddd9 base:constraint: Setting Configuration Bank Voltage Select
Set the properties to mirror the hardware configuration so
the Vivado tools can provide warnings if there are any conflicts
between configuration pin settings, such as an IOSTANDARD
on a multi-function configuration pin that conflicts with the
configuration voltage.
see:
https://www.xilinx.com/support/documentation/user_guides/ug570-ultrascale-configuration.pdf

The following base constraints were updated:
 - kcu105
 - kc705
 - vc707
 - ac701
2018-04-11 15:09:54 +03:00
..
a10gx a10gx: Force all used tiles to high speed, in order to improve timing 2017-10-04 16:16:00 +01:00
a10soc avl_dacfifo: Refactor the fifo 2017-10-31 14:30:06 +00:00
ac701 base:constraint: Setting Configuration Bank Voltage Select 2018-04-11 15:09:54 +03:00
altera altera- 2017-r1 16.1.2 2017-05-30 12:21:27 -04:00
c5soc Remove executable flag from non-executable files 2017-07-28 17:56:07 +02:00
kc705 base:constraint: Setting Configuration Bank Voltage Select 2018-04-11 15:09:54 +03:00
kcu105 base:constraint: Setting Configuration Bank Voltage Select 2018-04-11 15:09:54 +03:00
microzed common/microzed: Enable PS CLK1 = 200MHz 2017-09-25 15:16:58 +03:00
mitx045 Remove executable flag from non-executable files 2017-07-28 17:56:07 +02:00
vc707 base:constraint: Setting Configuration Bank Voltage Select 2018-04-11 15:09:54 +03:00
xilinx xilinx- ad-ip-instance & ad-ip-parameter 2017-04-06 13:04:19 -04:00
zc702 projects/zc702- free pmod gpio for customization 2017-08-09 14:06:26 -04:00
zc706 plddr3_dacfifo_bd: Increase the AXI burst length to max 2017-07-06 10:15:06 +01:00
zcu102 common/zcu102: Fix ps8 ref clock 0 frequency assignament 2017-08-22 15:37:59 +03:00
zed common: zed/zc702/zc706/mitx045: audio_clkgen: Disable phase alignment 2017-04-20 18:12:24 +02:00
Makefile Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00