723 lines
22 KiB
Verilog
723 lines
22 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9361 #(
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// parameters
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parameter ID = 0,
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parameter MODE_1R1T = 0,
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parameter DEVICE_TYPE = 0,
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parameter TDD_DISABLE = 0,
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parameter PPS_RECEIVER_ENABLE = 0,
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parameter CMOS_OR_LVDS_N = 0,
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parameter ADC_INIT_DELAY = 0,
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parameter ADC_DATAPATH_DISABLE = 0,
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parameter ADC_USERPORTS_DISABLE = 0,
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parameter ADC_DATAFORMAT_DISABLE = 0,
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parameter ADC_DCFILTER_DISABLE = 0,
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parameter ADC_IQCORRECTION_DISABLE = 0,
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parameter DAC_INIT_DELAY = 0,
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parameter DAC_CLK_EDGE_SEL = 0,
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parameter DAC_IODELAY_ENABLE = 0,
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parameter DAC_DATAPATH_DISABLE = 0,
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parameter DAC_DDS_DISABLE = 0,
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parameter DAC_USERPORTS_DISABLE = 0,
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parameter DAC_IQCORRECTION_DISABLE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group") (
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// physical interface (receive-lvds)
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input rx_clk_in_p,
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input rx_clk_in_n,
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input rx_frame_in_p,
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input rx_frame_in_n,
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input [ 5:0] rx_data_in_p,
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input [ 5:0] rx_data_in_n,
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// physical interface (receive-cmos)
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input rx_clk_in,
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input rx_frame_in,
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input [11:0] rx_data_in,
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// physical interface (transmit-lvds)
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output tx_clk_out_p,
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output tx_clk_out_n,
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output tx_frame_out_p,
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output tx_frame_out_n,
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output [ 5:0] tx_data_out_p,
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output [ 5:0] tx_data_out_n,
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// physical interface (transmit-cmos)
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output tx_clk_out,
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output tx_frame_out,
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output [11:0] tx_data_out,
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// ensm control
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output enable,
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output txnrx,
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// transmit master/slave
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input dac_sync_in,
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output dac_sync_out,
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// tdd sync
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input tdd_sync,
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output tdd_sync_cntr,
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input gps_pps,
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output gps_pps_irq,
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// delay clock
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input delay_clk,
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// master interface
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output l_clk,
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input clk,
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output rst,
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// dma interface
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output adc_enable_i0,
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output adc_valid_i0,
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output [15:0] adc_data_i0,
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output adc_enable_q0,
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output adc_valid_q0,
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output [15:0] adc_data_q0,
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output adc_enable_i1,
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output adc_valid_i1,
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output [15:0] adc_data_i1,
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output adc_enable_q1,
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output adc_valid_q1,
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output [15:0] adc_data_q1,
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input adc_dovf,
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input adc_dunf,
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output adc_r1_mode,
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output dac_enable_i0,
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output dac_valid_i0,
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input [15:0] dac_data_i0,
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output dac_enable_q0,
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output dac_valid_q0,
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input [15:0] dac_data_q0,
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output dac_enable_i1,
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output dac_valid_i1,
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input [15:0] dac_data_i1,
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output dac_enable_q1,
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output dac_valid_q1,
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input [15:0] dac_data_q1,
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input dac_dovf,
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input dac_dunf,
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output dac_r1_mode,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready,
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// gpio
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input up_enable,
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input up_txnrx,
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input [31:0] up_dac_gpio_in,
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output [31:0] up_dac_gpio_out,
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input [31:0] up_adc_gpio_in,
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output [31:0] up_adc_gpio_out);
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// derived parameters
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localparam ADC_USERPORTS_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_USERPORTS_DISABLE;
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localparam ADC_DATAFORMAT_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DATAFORMAT_DISABLE;
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localparam ADC_DCFILTER_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DCFILTER_DISABLE;
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localparam ADC_IQCORRECTION_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_IQCORRECTION_DISABLE;
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localparam DAC_DDS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_DDS_DISABLE;
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localparam DAC_USERPORTS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_USERPORTS_DISABLE;
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localparam DAC_DELAYCNTRL_DISABLE_INT = (DAC_IODELAY_ENABLE == 1) ? 0 : 1;
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localparam DAC_IQCORRECTION_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_IQCORRECTION_DISABLE;
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// internal registers
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reg adc_valid_i0_int = 'd0;
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reg adc_valid_q0_int = 'd0;
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reg adc_valid_i1_int = 'd0;
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reg adc_valid_q1_int = 'd0;
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reg [15:0] adc_data_i0_int = 'd0;
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reg [15:0] adc_data_q0_int = 'd0;
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reg [15:0] adc_data_i1_int = 'd0;
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reg [15:0] adc_data_q1_int = 'd0;
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reg dac_valid_i0_int = 'd0;
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reg dac_valid_q0_int = 'd0;
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reg dac_valid_i1_int = 'd0;
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reg dac_valid_q1_int = 'd0;
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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reg [31:0] up_rdata = 'd0;
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// internal clocks and resets
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wire up_clk;
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wire up_rstn;
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wire mmcm_rst;
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wire delay_rst;
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// internal signals
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wire adc_ddr_edgesel_s;
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wire adc_valid_s;
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wire adc_valid_i0_s;
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wire adc_valid_q0_s;
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wire adc_valid_i1_s;
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wire adc_valid_q1_s;
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wire [15:0] adc_data_i0_s;
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wire [15:0] adc_data_q0_s;
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wire [15:0] adc_data_i1_s;
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wire [15:0] adc_data_q1_s;
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wire [47:0] adc_data_s;
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wire adc_status_s;
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wire dac_clksel_s;
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wire dac_valid_s;
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wire [47:0] dac_data_s;
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wire dac_valid_i0_s;
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wire dac_valid_q0_s;
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wire dac_valid_i1_s;
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wire dac_valid_q1_s;
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wire dac_data_i0_s;
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wire dac_data_q0_s;
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wire dac_data_i1_s;
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wire dac_data_q1_s;
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wire [12:0] up_adc_dld_s;
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wire [64:0] up_adc_dwdata_s;
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wire [64:0] up_adc_drdata_s;
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wire [15:0] up_dac_dld_s;
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wire [79:0] up_dac_dwdata_s;
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wire [79:0] up_dac_drdata_s;
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wire delay_locked_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_rx_s;
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wire up_wack_tx_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_rx_s;
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wire up_rack_rx_s;
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wire [31:0] up_rdata_tx_s;
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wire up_rack_tx_s;
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wire up_wack_tdd_s;
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wire up_rack_tdd_s;
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wire [31:0] up_rdata_tdd_s;
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wire tdd_enable_s;
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wire tdd_txnrx_s;
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wire tdd_mode_s;
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wire tdd_tx_valid_s;
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wire tdd_rx_valid_s;
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wire tdd_rx_vco_en_s;
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wire tdd_tx_vco_en_s;
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wire tdd_rx_rf_en_s;
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wire tdd_tx_rf_en_s;
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wire [ 7:0] tdd_status_s;
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wire up_drp_sel;
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wire up_drp_wr;
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wire [11:0] up_drp_addr;
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wire [31:0] up_drp_wdata;
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wire [31:0] up_drp_rdata;
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wire up_drp_ready;
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wire up_drp_locked;
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wire [31:0] up_pps_rcounter_s;
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wire up_pps_status_s;
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wire up_irq_mask_s;
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wire adc_up_pps_irq_mask_s;
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wire dac_up_pps_irq_mask_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack <= 'd0;
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_wack <= up_wack_rx_s | up_wack_tx_s | up_wack_tdd_s;
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up_rack <= up_rack_rx_s | up_rack_tx_s | up_rack_tdd_s;
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up_rdata <= up_rdata_rx_s | up_rdata_tx_s | up_rdata_tdd_s;
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end
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end
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// device interface
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generate
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if (CMOS_OR_LVDS_N == 1) begin
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assign tx_clk_out_p = 1'd0;
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assign tx_clk_out_n = 1'd1;
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assign tx_frame_out_p = 1'd0;
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assign tx_frame_out_n = 1'd0;
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assign tx_data_out_p = 6'h00;
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assign tx_data_out_n = 6'h3f;
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axi_ad9361_cmos_if #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
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.IO_DELAY_GROUP (IO_DELAY_GROUP))
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i_dev_if (
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.rx_clk_in (rx_clk_in),
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.rx_frame_in (rx_frame_in),
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.rx_data_in (rx_data_in),
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.tx_clk_out (tx_clk_out),
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.tx_frame_out (tx_frame_out),
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.tx_data_out (tx_data_out),
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.enable (enable),
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.txnrx (txnrx),
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.rst (rst),
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.clk (clk),
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.l_clk (l_clk),
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.adc_valid (adc_valid_s),
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.adc_data (adc_data_s),
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.adc_status (adc_status_s),
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.adc_r1_mode (adc_r1_mode),
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.adc_ddr_edgesel (adc_ddr_edgesel_s),
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.dac_valid (dac_valid_s),
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.dac_data (dac_data_s),
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.dac_clksel (dac_clksel_s),
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.dac_r1_mode (dac_r1_mode),
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.tdd_enable (tdd_enable_s),
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.tdd_txnrx (tdd_txnrx_s),
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.tdd_mode (tdd_mode_s),
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.mmcm_rst (mmcm_rst),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_enable (up_enable),
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.up_txnrx (up_txnrx),
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.up_adc_dld (up_adc_dld_s),
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.up_adc_dwdata (up_adc_dwdata_s),
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.up_adc_drdata (up_adc_drdata_s),
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.up_dac_dld (up_dac_dld_s),
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.up_dac_dwdata (up_dac_dwdata_s),
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.up_dac_drdata (up_dac_drdata_s),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked_s),
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.up_drp_sel (up_drp_sel),
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.up_drp_wr (up_drp_wr),
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.up_drp_addr (up_drp_addr),
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.up_drp_wdata (up_drp_wdata),
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.up_drp_rdata (up_drp_rdata),
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.up_drp_ready (up_drp_ready),
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.up_drp_locked(up_drp_locked));
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end
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endgenerate
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generate
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if (CMOS_OR_LVDS_N == 0) begin
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assign tx_clk_out = 1'd0;
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assign tx_frame_out = 1'd0;
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assign tx_data_out = 12'd0;
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assign up_adc_drdata_s[64:35] = 30'd0;
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assign up_dac_drdata_s[79:50] = 30'd0;
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axi_ad9361_lvds_if #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE),
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.IO_DELAY_GROUP (IO_DELAY_GROUP))
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i_dev_if (
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.rx_clk_in_p (rx_clk_in_p),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_data_in_n (rx_data_in_n),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_data_out_p (tx_data_out_p),
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.tx_data_out_n (tx_data_out_n),
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.enable (enable),
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.txnrx (txnrx),
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.rst (rst),
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.clk (clk),
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.l_clk (l_clk),
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.adc_valid (adc_valid_s),
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.adc_data (adc_data_s),
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.adc_status (adc_status_s),
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.adc_r1_mode (adc_r1_mode),
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.adc_ddr_edgesel (adc_ddr_edgesel_s),
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.dac_valid (dac_valid_s),
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.dac_data (dac_data_s),
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.dac_clksel (dac_clksel_s),
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.dac_r1_mode (dac_r1_mode),
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.tdd_enable (tdd_enable_s),
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.tdd_txnrx (tdd_txnrx_s),
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.tdd_mode (tdd_mode_s),
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.mmcm_rst (mmcm_rst),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_enable (up_enable),
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.up_txnrx (up_txnrx),
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.up_adc_dld (up_adc_dld_s[6:0]),
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.up_adc_dwdata (up_adc_dwdata_s[34:0]),
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.up_adc_drdata (up_adc_drdata_s[34:0]),
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.up_dac_dld (up_dac_dld_s[9:0]),
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.up_dac_dwdata (up_dac_dwdata_s[49:0]),
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.up_dac_drdata (up_dac_drdata_s[49:0]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked_s),
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.up_drp_sel (up_drp_sel),
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.up_drp_wr (up_drp_wr),
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.up_drp_addr (up_drp_addr),
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.up_drp_wdata (up_drp_wdata),
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.up_drp_rdata (up_drp_rdata),
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.up_drp_ready (up_drp_ready),
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.up_drp_locked(up_drp_locked));
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end
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endgenerate
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assign adc_valid_i0 = adc_valid_i0_int;
|
|
assign adc_valid_q0 = adc_valid_q0_int;
|
|
assign adc_valid_i1 = adc_valid_i1_int;
|
|
assign adc_valid_q1 = adc_valid_q1_int;
|
|
|
|
always @(posedge clk) begin
|
|
adc_valid_i0_int <= tdd_rx_valid_s & adc_valid_i0_s;
|
|
adc_valid_q0_int <= tdd_rx_valid_s & adc_valid_q0_s;
|
|
adc_valid_i1_int <= tdd_rx_valid_s & adc_valid_i1_s;
|
|
adc_valid_q1_int <= tdd_rx_valid_s & adc_valid_q1_s;
|
|
end
|
|
|
|
assign adc_data_i0 = adc_data_i0_int;
|
|
assign adc_data_q0 = adc_data_q0_int;
|
|
assign adc_data_i1 = adc_data_i1_int;
|
|
assign adc_data_q1 = adc_data_q1_int;
|
|
|
|
always @(posedge clk) begin
|
|
adc_data_i0_int <= adc_data_i0_s;
|
|
adc_data_q0_int <= adc_data_q0_s;
|
|
adc_data_i1_int <= adc_data_i1_s;
|
|
adc_data_q1_int <= adc_data_q1_s;
|
|
end
|
|
|
|
assign dac_valid_i0 = dac_valid_i0_int;
|
|
assign dac_valid_q0 = dac_valid_q0_int;
|
|
assign dac_valid_i1 = dac_valid_i1_int;
|
|
assign dac_valid_q1 = dac_valid_q1_int;
|
|
|
|
always @(posedge clk) begin
|
|
dac_valid_i0_int <= tdd_tx_valid_s & dac_valid_i0_s;
|
|
dac_valid_q0_int <= tdd_tx_valid_s & dac_valid_q0_s;
|
|
dac_valid_i1_int <= tdd_tx_valid_s & dac_valid_i1_s;
|
|
dac_valid_q1_int <= tdd_tx_valid_s & dac_valid_q1_s;
|
|
end
|
|
|
|
// tdd
|
|
|
|
generate
|
|
if (TDD_DISABLE == 1) begin
|
|
assign tdd_enable_s = 1'b0;
|
|
assign tdd_txnrx_s = 1'b0;
|
|
assign tdd_txnrx_s = 1'b0;
|
|
assign tdd_mode_s = 1'b0;
|
|
assign tdd_rx_vco_en_s = 1'b0;
|
|
assign tdd_tx_vco_en_s = 1'b0;
|
|
assign tdd_rx_rf_en_s = 1'b0;
|
|
assign tdd_tx_rf_en_s = 1'b0;
|
|
assign tdd_status_s = 8'd0;
|
|
assign tdd_sync_cntr = 1'b0;
|
|
assign tdd_tx_valid_s = 1'b1;
|
|
assign tdd_rx_valid_s = 1'b1;
|
|
assign up_wack_tdd_s = 1'b0;
|
|
assign up_rack_tdd_s = 1'b0;
|
|
assign up_rdata_tdd_s = 32'b0;
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (TDD_DISABLE == 0) begin
|
|
axi_ad9361_tdd_if #(.LEVEL_OR_PULSE_N(1)) i_tdd_if (
|
|
.clk (clk),
|
|
.rst (rst),
|
|
.tdd_rx_vco_en (tdd_rx_vco_en_s),
|
|
.tdd_tx_vco_en (tdd_tx_vco_en_s),
|
|
.tdd_rx_rf_en (tdd_rx_rf_en_s),
|
|
.tdd_tx_rf_en (tdd_tx_rf_en_s),
|
|
.ad9361_txnrx (tdd_txnrx_s),
|
|
.ad9361_enable (tdd_enable_s),
|
|
.ad9361_tdd_status (tdd_status_s));
|
|
|
|
axi_ad9361_tdd i_tdd (
|
|
.clk (clk),
|
|
.rst (rst),
|
|
.tdd_rx_vco_en (tdd_rx_vco_en_s),
|
|
.tdd_tx_vco_en (tdd_tx_vco_en_s),
|
|
.tdd_rx_rf_en (tdd_rx_rf_en_s),
|
|
.tdd_tx_rf_en (tdd_tx_rf_en_s),
|
|
.tdd_enabled (tdd_mode_s),
|
|
.tdd_status (tdd_status_s),
|
|
.tdd_sync (tdd_sync),
|
|
.tdd_sync_cntr (tdd_sync_cntr),
|
|
.tdd_tx_valid (tdd_tx_valid_s),
|
|
.tdd_rx_valid (tdd_rx_valid_s),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_wreq (up_wreq_s),
|
|
.up_waddr (up_waddr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_wack (up_wack_tdd_s),
|
|
.up_rreq (up_rreq_s),
|
|
.up_raddr (up_raddr_s),
|
|
.up_rdata (up_rdata_tdd_s),
|
|
.up_rack (up_rack_tdd_s));
|
|
end
|
|
endgenerate
|
|
|
|
generate if (PPS_RECEIVER_ENABLE == 1) begin
|
|
// GPS's PPS receiver
|
|
ad_pps_receiver i_pps_receiver (
|
|
.clk (clk),
|
|
.rst (rst),
|
|
.gps_pps (gps_pps),
|
|
.up_clk (up_clk),
|
|
.up_rstn (up_rstn),
|
|
.up_pps_rcounter (up_pps_rcounter_s),
|
|
.up_pps_status (up_pps_status_s),
|
|
.up_irq_mask (up_irq_mask_s),
|
|
.up_irq (gps_pps_irq));
|
|
assign up_irq_mask_s = adc_up_pps_irq_mask_s | dac_up_pps_irq_mask_s;
|
|
end
|
|
endgenerate
|
|
|
|
generate if (PPS_RECEIVER_ENABLE == 0) begin
|
|
assign up_pps_rcounter_s = 32'b0;
|
|
assign up_pps_status_s = 1'b1;
|
|
assign gps_pps_irq = 1'b0;
|
|
end
|
|
endgenerate
|
|
|
|
// receive
|
|
|
|
axi_ad9361_rx #(
|
|
.ID (ID),
|
|
.MODE_1R1T (MODE_1R1T),
|
|
.CMOS_OR_LVDS_N (CMOS_OR_LVDS_N),
|
|
.PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE),
|
|
.INIT_DELAY (ADC_INIT_DELAY),
|
|
.USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT),
|
|
.DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT),
|
|
.DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT),
|
|
.IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT))
|
|
i_rx (
|
|
.mmcm_rst (mmcm_rst),
|
|
.adc_rst (rst),
|
|
.adc_clk (clk),
|
|
|
|
.adc_valid (adc_valid_s),
|
|
.adc_data (adc_data_s),
|
|
.adc_status (adc_status_s),
|
|
.adc_r1_mode (adc_r1_mode),
|
|
.adc_ddr_edgesel (adc_ddr_edgesel_s),
|
|
.dac_data (dac_data_s),
|
|
.up_dld (up_adc_dld_s),
|
|
.up_dwdata (up_adc_dwdata_s),
|
|
.up_drdata (up_adc_drdata_s),
|
|
.delay_clk (delay_clk),
|
|
.delay_rst (delay_rst),
|
|
.delay_locked (delay_locked_s),
|
|
.adc_enable_i0 (adc_enable_i0),
|
|
.adc_valid_i0 (adc_valid_i0_s),
|
|
.adc_data_i0 (adc_data_i0_s),
|
|
.adc_enable_q0 (adc_enable_q0),
|
|
.adc_valid_q0 (adc_valid_q0_s),
|
|
.adc_data_q0 (adc_data_q0_s),
|
|
.adc_enable_i1 (adc_enable_i1),
|
|
.adc_valid_i1 (adc_valid_i1_s),
|
|
.adc_data_i1 (adc_data_i1_s),
|
|
.adc_enable_q1 (adc_enable_q1),
|
|
.adc_valid_q1 (adc_valid_q1_s),
|
|
.adc_data_q1 (adc_data_q1_s),
|
|
.adc_dovf (adc_dovf),
|
|
.adc_dunf (adc_dunf),
|
|
.up_adc_gpio_in (up_adc_gpio_in),
|
|
.up_adc_gpio_out (up_adc_gpio_out),
|
|
.up_pps_rcounter (up_pps_rcounter_s),
|
|
.up_pps_status (up_pps_status_s),
|
|
.up_pps_irq_mask (adc_up_pps_irq_mask_s),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_wreq (up_wreq_s),
|
|
.up_waddr (up_waddr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_wack (up_wack_rx_s),
|
|
.up_rreq (up_rreq_s),
|
|
.up_raddr (up_raddr_s),
|
|
.up_rdata (up_rdata_rx_s),
|
|
.up_rack (up_rack_rx_s),
|
|
.up_drp_sel (up_drp_sel),
|
|
.up_drp_wr (up_drp_wr),
|
|
.up_drp_addr (up_drp_addr),
|
|
.up_drp_wdata (up_drp_wdata),
|
|
.up_drp_rdata (up_drp_rdata),
|
|
.up_drp_ready (up_drp_ready),
|
|
.up_drp_locked(up_drp_locked));
|
|
|
|
// transmit
|
|
|
|
axi_ad9361_tx #(
|
|
.ID (ID),
|
|
.MODE_1R1T (MODE_1R1T),
|
|
.CLK_EDGE_SEL (DAC_CLK_EDGE_SEL),
|
|
.CMOS_OR_LVDS_N (CMOS_OR_LVDS_N),
|
|
.PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE),
|
|
.INIT_DELAY (DAC_INIT_DELAY),
|
|
.DDS_DISABLE (DAC_DDS_DISABLE_INT),
|
|
.USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT),
|
|
.DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT),
|
|
.IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT))
|
|
i_tx (
|
|
.dac_clk (clk),
|
|
.dac_valid (dac_valid_s),
|
|
.dac_data (dac_data_s),
|
|
.dac_clksel (dac_clksel_s),
|
|
.dac_r1_mode (dac_r1_mode),
|
|
.adc_data (adc_data_s),
|
|
.up_dld (up_dac_dld_s),
|
|
.up_dwdata (up_dac_dwdata_s),
|
|
.up_drdata (up_dac_drdata_s),
|
|
.delay_clk (delay_clk),
|
|
.delay_rst (),
|
|
.delay_locked (delay_locked_s),
|
|
.dac_sync_in (dac_sync_in),
|
|
.dac_sync_out (dac_sync_out),
|
|
.dac_enable_i0 (dac_enable_i0),
|
|
.dac_valid_i0 (dac_valid_i0_s),
|
|
.dac_data_i0 (dac_data_i0),
|
|
.dac_enable_q0 (dac_enable_q0),
|
|
.dac_valid_q0 (dac_valid_q0_s),
|
|
.dac_data_q0 (dac_data_q0),
|
|
.dac_enable_i1 (dac_enable_i1),
|
|
.dac_valid_i1 (dac_valid_i1_s),
|
|
.dac_data_i1 (dac_data_i1),
|
|
.dac_enable_q1 (dac_enable_q1),
|
|
.dac_valid_q1 (dac_valid_q1_s),
|
|
.dac_data_q1 (dac_data_q1),
|
|
.dac_dovf(dac_dovf),
|
|
.dac_dunf(dac_dunf),
|
|
.up_pps_rcounter (up_pps_rcounter_s),
|
|
.up_pps_status (up_pps_status_s),
|
|
.up_pps_irq_mask (dac_up_pps_irq_mask_s),
|
|
.up_dac_gpio_in (up_dac_gpio_in),
|
|
.up_dac_gpio_out (up_dac_gpio_out),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_wreq (up_wreq_s),
|
|
.up_waddr (up_waddr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_wack (up_wack_tx_s),
|
|
.up_rreq (up_rreq_s),
|
|
.up_raddr (up_raddr_s),
|
|
.up_rdata (up_rdata_tx_s),
|
|
.up_rack (up_rack_tx_s));
|
|
|
|
// axi interface
|
|
|
|
up_axi i_up_axi (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_axi_awvalid (s_axi_awvalid),
|
|
.up_axi_awaddr (s_axi_awaddr),
|
|
.up_axi_awready (s_axi_awready),
|
|
.up_axi_wvalid (s_axi_wvalid),
|
|
.up_axi_wdata (s_axi_wdata),
|
|
.up_axi_wstrb (s_axi_wstrb),
|
|
.up_axi_wready (s_axi_wready),
|
|
.up_axi_bvalid (s_axi_bvalid),
|
|
.up_axi_bresp (s_axi_bresp),
|
|
.up_axi_bready (s_axi_bready),
|
|
.up_axi_arvalid (s_axi_arvalid),
|
|
.up_axi_araddr (s_axi_araddr),
|
|
.up_axi_arready (s_axi_arready),
|
|
.up_axi_rvalid (s_axi_rvalid),
|
|
.up_axi_rresp (s_axi_rresp),
|
|
.up_axi_rdata (s_axi_rdata),
|
|
.up_axi_rready (s_axi_rready),
|
|
.up_wreq (up_wreq_s),
|
|
.up_waddr (up_waddr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_wack (up_wack),
|
|
.up_rreq (up_rreq_s),
|
|
.up_raddr (up_raddr_s),
|
|
.up_rdata (up_rdata),
|
|
.up_rack (up_rack));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|