Laszlo Nagy b6d2def504 axi_ad9361: clear synthesis warnings ... Defined the delay registers only when they are used.		2018-04-11 15:09:54 +03:00
..
altera	axi_ad9361: Fix the last incorrect merge	2017-10-03 09:15:23 +01:00
xilinx	axi_ad9361: xilinx LVDS interface: Restore previous feedback clock polarity	2018-01-19 18:17:50 +01:00
Makefile	hdlmake.pl- updates	2017-08-07 16:09:20 -04:00
axi_ad9361.v	axi_ad9361: Fix incorrect merge	2017-10-03 10:51:35 +01:00
axi_ad9361_constr.sdc	library/axi_ad9361: tdd false paths	2016-05-04 13:42:12 -04:00
axi_ad9361_constr.xdc	axi_ad9361: Update constraint file	2017-08-04 16:20:33 +01:00
axi_ad9361_delay.tcl	move/rename - delay script belongs to ad9361	2017-03-10 12:44:32 -05:00
axi_ad9361_hw.tcl	axi_ad9361: Fix the last incorrect merge	2017-10-03 09:15:23 +01:00
axi_ad9361_ip.tcl	axi_*: Infer clock and reset signals of an IP	2018-04-11 15:09:54 +03:00
axi_ad9361_rx.v	axi_*: Fix instantiation of up_[adc|dac]_[common|channel]	2018-04-11 15:09:54 +03:00
axi_ad9361_rx_channel.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00
axi_ad9361_rx_pnmon.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00
axi_ad9361_tdd.v	license: Add some clarification to the header license	2017-05-31 18:18:56 +03:00
axi_ad9361_tdd_if.v	axi_ad9361: clear synthesis warnings	2018-04-11 15:09:54 +03:00
axi_ad9361_tx.v	axi_*: Fix instantiation of up_[adc|dac]_[common|channel]	2018-04-11 15:09:54 +03:00
axi_ad9361_tx_channel.v	axi_*: Fix instantiation of up_[adc|dac]_[common|channel]	2018-04-11 15:09:54 +03:00