176 lines
5.4 KiB
Verilog
176 lines
5.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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input sys_clk,
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input sys_resetn,
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// ddr3
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output ddr3_clk_p,
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output ddr3_clk_n,
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output [ 14:0] ddr3_a,
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output [ 2:0] ddr3_ba,
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output ddr3_cke,
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output ddr3_cs_n,
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output ddr3_odt,
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output ddr3_reset_n,
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output ddr3_we_n,
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output ddr3_ras_n,
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output ddr3_cas_n,
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inout [ 7:0] ddr3_dqs_p,
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inout [ 7:0] ddr3_dqs_n,
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inout [ 63:0] ddr3_dq,
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output [ 7:0] ddr3_dm,
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input ddr3_rzq,
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input ddr3_ref_clk,
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// ethernet
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input eth_ref_clk,
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input eth_rxd,
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output eth_txd,
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output eth_mdc,
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inout eth_mdio,
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output eth_resetn,
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input eth_intn,
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// board gpio
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input [ 10:0] gpio_bd_i,
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output [ 15:0] gpio_bd_o,
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// daq1 interface
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input dac_clk_in,
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output dac_clk_out,
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output dac_frame_out,
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output [15:0] dac_data_out,
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input adc_clk_in,
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input [13:0] adc_data_in,
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output spi_clk,
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output spi_csn,
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inout spi_sdio,
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input spi_int);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire spi_mosi;
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wire spi_miso;
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// board specific connections
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assign eth_resetn = ~eth_reset;
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assign eth_mdio_i = eth_mdio;
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assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
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assign ddr3_a[14:12] = 3'd0;
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assign gpio_i[31:27] = gpio_o[31:27];
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assign gpio_i[26:16] = gpio_bd_i;
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assign gpio_i[15: 0] = gpio_o[15:0];
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assign gpio_bd_o = gpio_o[15:0];
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// instantiations
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daq1_spi i_spi (
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.spi_csn (spi_csn),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio));
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system_bd i_system_bd (
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.sys_clk_clk (sys_clk),
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.sys_rst_reset_n (sys_resetn),
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.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
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.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
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.sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
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.sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
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.sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
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.sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
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.sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
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.sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
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.sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
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.sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
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.sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
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.sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
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.sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
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.sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
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.sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
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.sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
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.sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
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.sys_ethernet_mdio_mdc (eth_mdc),
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.sys_ethernet_mdio_mdio_in (eth_mdio_i),
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.sys_ethernet_mdio_mdio_out (eth_mdio_o),
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.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
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.sys_ethernet_ref_clk_clk (eth_ref_clk),
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.sys_ethernet_reset_reset (eth_reset),
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.sys_ethernet_sgmii_rxp_0 (eth_rxd),
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.sys_ethernet_sgmii_txp_0 (eth_txd),
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.sys_gpio_bd_in_port (gpio_i[31:0]),
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.sys_gpio_bd_out_port (gpio_o[31:0]),
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.sys_gpio_in_export (gpio_i[63:32]),
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.sys_gpio_out_export (gpio_o[63:32]),
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.sys_spi_MISO (spi_miso),
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.sys_spi_MOSI (spi_mosi),
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.sys_spi_SCLK (spi_clk),
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.sys_spi_SS_n (spi_csn),
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.spi_int_irq(spi_int),
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.axi_ad9684_device_if_adc_clk_in_n (1'd0),
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.axi_ad9684_device_if_adc_clk_in_p (adc_clk_in),
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.axi_ad9684_device_if_adc_data_in_n (14'd0),
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.axi_ad9684_device_if_adc_data_in_p (adc_data_in),
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.axi_ad9122_device_if_dac_clk_in_n (1'd0),
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.axi_ad9122_device_if_dac_clk_in_p (dac_clk_in),
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.axi_ad9122_device_if_dac_clk_out_n (),
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.axi_ad9122_device_if_dac_clk_out_p (dac_clk_out),
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.axi_ad9122_device_if_dac_data_out_n (),
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.axi_ad9122_device_if_dac_data_out_p (dac_data_out),
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.axi_ad9122_device_if_dac_frame_out_n (),
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.axi_ad9122_device_if_dac_frame_out_p (dac_frame_out)
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);
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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