a3cd70ff1d
This commit fixes the following warning from the IP packaging flow: "[IP_Flow 19-801] The last file in file group "Synthesis" should be an HDL file: "axi_dmac_constr.ttcl". During generation the IP Flow uses the last file to determine library and other information when generating the top wrapper file. If possible, please make sure that non-HDL files are located earlier in the list of files for this file group." Having the ttcl or other non HDL file at the end of the file group causes issues when the project preferred language is set to VHDL. Since the synthesis file group is set to "xilinx_anylanguagesynthesis" the tool tries to guess the type of wrapper to be generated for that IP based on the last file from the file group. If the file is non HDL then he defaults to the preferred language (this case VHDL) Due some issue when the tool tries to create a VHDL wrapper for an IP that has a Verilog top file with boolean parameters set from the IP packager he fails. After we reorder the files after each non HDL file addition he will create a correct Verilog wrapper for it with all parameters which can be integrated in a VHDL system top file without issues. |
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| library | ||
| projects | ||
| .gitattributes | ||
| .gitignore | ||
| LICENSE | ||
| LICENSE_ADIBSD | ||
| LICENSE_GPL2 | ||
| LICENSE_LGPL | ||
| Makefile | ||
| README.md | ||
| quiet.mk | ||
README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects.
Getting started
This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.
Prerequisites
or
Please make sure that you have the required tool version.
How to build a project
For building a projects, you have to use the GNU Make tool. If you're a Windows user please checkout this page, to see how you can install this tool.
To build a project, checkout the latest release, after that just cd to the project that you want to build and run make:
[~]cd projects/fmcomms2/zc706
[~]make
A more comprehensive build guide can be found under the following link: https://wiki.analog.com/resources/fpga/docs/build
Software
In general all the projects have no-OS (baremetal) and a Linux support. See no-OS or Linux for more information.
Which branch should I use?
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If you want to use the most stable code base, always use the latest release branch.
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If you want to use the greatest and latest, check out the master branch.
License
In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.
The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.
See LICENSE for more details. The separate license files cab be found here:
Comprehensive user guide
See HDL User Guide for a more detailed guide.
Support
Feel free to ask any question at EngineerZone.