21 lines
582 B
Tcl
21 lines
582 B
Tcl
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## FIFO depth is 8Mb - 500k samples
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set adc_fifo_name axi_ad9680_fifo
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set adc_fifo_address_width 17
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set adc_data_width 128
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set adc_dma_data_width 64
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## FIFO depth is 8Mb - 500k samples
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set dac_fifo_name axi_ad9144_fifo
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set dac_fifo_address_width 16
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set dac_data_width 128
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set dac_dma_data_width 128
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## NOTE: With this configuration the #36Kb BRAM utilization is at ~68.45%
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source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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source ../common/daq2_bd.tcl
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