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Istvan Csomortani a290611c09 util_tdd_sync: Initial commit 
A synchronization signal generator for AD9361 running on TDD mode.
If the associated device is master, the module generates a pulse in a defined interval. Otherwise receives the sync signal from outside.
 		2015-11-11 10:46:11 +02:00
library util_tdd_sync: Initial commit 2015-11-11 10:46:11 +02:00
projects Makefiles: Update makefiles to include the nerw axi_gpreg / util_mfifo libraries 2015-11-10 09:32:50 +02:00
.gitattributes Add .gitattributes file 2015-06-26 11:07:10 +02:00
.gitignore ignore gui 2015-09-22 16:32:02 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update Vivado's version number 2015-09-29 15:11:10 +03:00

README.md

#HDL Reference Designs

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