a1539a62b7
The ad_mem_asym memory read interface has a 3 clock cycle delay, from the moment of the address change until a valid data arrives on the bus; because the dac_xfer_out is going to validate the outgoing samples (in conjunction with the DAC VALID, which is free a running signal), this module will compensate this delay, to prevent duplicated samples in the beginning of the transaction. |
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| .. | ||
| avl_dacfifo.v | ||
| avl_dacfifo_constr.sdc | ||
| avl_dacfifo_hw.tcl | ||
| avl_dacfifo_rd.v | ||
| avl_dacfifo_wr.v | ||