Adrian Costina 240b75cc45 fmcadc2: VC707, specifically connect spi_csn[2:0] to the fmcadc2_spi module		2018-09-05 15:53:18 +03:00
..
Makefile	Regenerate project Makefiles using the new shared Makefile includes	2018-04-11 15:09:54 +03:00
system_bd.tcl	adc|dac_fifo: Maximize the depth of each instance of the internal RAM FIFOs	2018-08-21 11:44:05 +03:00
system_constr.xdc	jesd_rst_gen:constraints: Remove invalid false path definitions	2018-04-11 15:09:54 +03:00
system_project.tcl	scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects	2017-06-07 12:06:50 +03:00
system_top.v	fmcadc2: VC707, specifically connect spi_csn[2:0] to the fmcadc2_spi module	2018-09-05 15:53:18 +03:00