169f38e7d1
The ad_ip_jesd204_tpl_dac currently only supports JESD204 modes that have both N and N' set to 16. Newer DACs like the AD9172 support modes where N and N' are not equal to 16. Add support for these modes. The width of the internal channel data path is set to N, only processing as many bits as necessary. At the framer the data is up-sized to N' bits with tail bits inserted as necessary. This data is then passed to the link layer. The width at the DMA interface is kept at 16 bits per sample regardless of the configuration of either N or N'. This is done to keep the interface consistent with the existing infrastructure it will connect to like upack and DMA. The data is expected to the LSB aligned, the unused MSBs will be ignored. Same is true for the test-pattern data registers. These register keep their existing 16-bit layout, but unused MSBs will be ignored by the core. The PN generators are modified to create only N bits of data per sample. Note that while the core can now support modes with N' = 12 there is still the restriction that requires the number of frames per beat to be an even number. Which means that not all modes with N' = 12 can be supported yet. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| Makefile | ||
| axi_ad9152.v | ||
| axi_ad9152_constr.xdc | ||
| axi_ad9152_hw.tcl | ||
| axi_ad9152_ip.tcl | ||