0caea39bad
In case when the SYSREF is connected to an FPGA IO which has a limitation on the IOB register IN_FF clock line and the required ref clock is high we can't use the IOB registers. e.g. the max clock rate on zcu102 HP IO FF is 312MHz but ref clock is 375MHz; If IOB is used in this case a pulse width violation is reported. This change makes the IOB placement selectable in such case or for targets which don't require class 1 operation. |
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| .. | ||
| Makefile | ||
| jesd204_tx.v | ||
| jesd204_tx_constr.sdc | ||
| jesd204_tx_constr.ttcl | ||
| jesd204_tx_ctrl.v | ||
| jesd204_tx_hw.tcl | ||
| jesd204_tx_ip.tcl | ||
| jesd204_tx_lane.v | ||