203 lines
6.2 KiB
Tcl
203 lines
6.2 KiB
Tcl
#-------------------------------------------------------------------------------
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# Processes for non-project mode development flow used for partial reconfiguration
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#-------------------------------------------------------------------------------
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# Initialize the workspace
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proc prcfg_init_workspace {prcfg_name_list} {
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# directory names
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set static_dir "prcfg_static"
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set sdk_dir "sdk_export"
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# make/clean all directory for design files
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if {![file exists $static_dir]} {
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file mkdir $static_dir
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} else {
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file delete -force $static_dir
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file mkdir $static_dir
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}
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foreach i $prcfg_name_list {
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if {![file exists prcfg_$i]} {
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file mkdir prcfg_$i
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} else {
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file delete -force prcfg_$i
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file mkdir prcfg_$i
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}
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}
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if {![file exists $sdk_dir]} {
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file mkdir $sdk_dir
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} else {
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file delete -force $sdk_dir
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file mkdir $sdk_dir
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}
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}
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# Create and synthesize the static part of the project
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proc prcfg_synth_static { verilog_files xdc_files } {
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global ad_hdl_dir
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global ad_phdl_dir
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global part
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# location of the generated block design file
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set system_project_dir ".srcs/sources_1/bd/system"
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# create project in mememory
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create_project -in_memory -part $part
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# setup repo for library
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set lib_dirs $ad_hdl_dir/library
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lappend lib_dirs $ad_phdl_dir/library
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set_property ip_repo_paths $lib_dirs [current_fileset]
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update_ip_catalog
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# create bd design
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create_bd_design "system"
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source system_bd.tcl
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generate_target all [get_files $system_project_dir/system.bd]
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make_wrapper -files [get_files $system_project_dir/system.bd] -top
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read_verilog $system_project_dir/hdl/system_wrapper.v
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# add project files
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read_verilog $verilog_files
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read_xdc $xdc_files
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# run shyntesis
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file mkdir "./prcfg_static/logs"
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synth_design -mode default -top system_top -part $part > "./prcfg_static/logs/synth_static.rds"
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# generate hardware specification file for sdk
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export_hardware [get_files .srcs/sources_1/bd/system/system.bd] -dir "./sdk_export"
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# write checkpoint
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file mkdir "./prcfg_static/checkpoints"
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write_checkpoint -force "./prcfg_static/checkpoints/synth_static.dcp"
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close_project
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}
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# Create and synthesize the reconfigurable part of the project
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proc prcfg_synth_reconf { prcfg_name verilog_files } {
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global ad_hdl_dir
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global ad_phdl_dir
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global part
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create_project -in_memory -part $part
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# add project files
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read_verilog $verilog_files
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# run OOC synthesis
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file mkdir "./prcfg_${prcfg_name}/logs"
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synth_design -mode out_of_context -top "prcfg_system_top" -part $part > "./prcfg_${prcfg_name}/logs/synth_${prcfg_name}.rds"
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# write checkpoint
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file mkdir "./prcfg_${prcfg_name}/checkpoints"
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write_checkpoint -force "./prcfg_${prcfg_name}/checkpoints/synth_${prcfg_name}.dcp"
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close_project
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}
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# Make the implementation of the project
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proc prcfg_impl { xdc_file reconfig_name_list } {
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global part
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for { set i 0 } { $i < [llength $reconfig_name_list] } { incr i } {
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set prcfg_name [lindex $reconfig_name_list $i]
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if { $i == 0 } {
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open_checkpoint "./prcfg_static/checkpoints/synth_static.dcp" -part $part
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# Create the RP area on the fabric and load the default logic on it
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read_xdc $xdc_file
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read_checkpoint -cell i_prcfg_system_top "./prcfg_${prcfg_name}/checkpoints/synth_${prcfg_name}.dcp"
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set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg_system_top]
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# implement the first configurations
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opt_design > "./prcfg_${prcfg_name}/logs/opt_${prcfg_name}.rds"
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# generate ltx file for debug probes
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write_debug_probes -force "./debug_nets.ltx"
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place_design > "./prcfg_${prcfg_name}/logs/place_${prcfg_name}.rds"
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route_design > "./prcfg_${prcfg_name}/logs/route_${prcfg_name}.rds"
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# save results
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save_results $prcfg_name
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# clear out RM
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update_design -cell i_prcfg_system_top -black_box
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# save static-only route
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write_checkpoint -force "./prcfg_static/checkpoints/route_static_only.dcp"
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close_project
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} else {
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open_checkpoint "./prcfg_static/checkpoints/route_static_only.dcp" -part $part
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# implement the next configuration
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# with the static-only design loaded in memory, lock down all placement and route
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lock_design -level routing
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read_checkpoint -cell i_prcfg_system_top "./prcfg_${prcfg_name}/checkpoints/synth_${prcfg_name}.dcp"
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opt_design > "./prcfg_${prcfg_name}/logs/opt_${prcfg_name}.rds"
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place_design > "./prcfg_${prcfg_name}/logs/place_${prcfg_name}.rds"
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route_design > "./prcfg_${prcfg_name}/logs/route_${prcfg_name}.rds"
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# save results
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save_results $prcfg_name
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close_project
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}
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}
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}
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# Save the result of an implementation, generate reports
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proc save_results { prcfg_name } {
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file mkdir "./prcfg_${prcfg_name}/results"
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# checkpoint to the routed design
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write_checkpoint -force "./prcfg_${prcfg_name}/results/top_route_design.dcp"
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# reports
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report_utilization -file "./prcfg_${prcfg_name}/results/top_utilization.rpt"
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report_timing_summary -file "./prcfg_${prcfg_name}/results/top_timing_summary.rpt"
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# checkpoint to the routed RP
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write_checkpoint -force -cell i_prcfg_system_top "./prcfg_${prcfg_name}/checkpoints/route_rm_${prcfg_name}.dcp"
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}
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# Verify the compatibility of different configurations
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proc prcfg_verify { prcfg_name_list } {
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set counter 0
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set list_length [llength $prcfg_name_list]
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file mkdir "./verify_design"
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for {set i 0} {$i < [expr $list_length - 1]} {incr i} {
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for {set j [expr $i + 1]} {$j < $list_length} {incr j} {
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set prcfg_name_a [lindex $prcfg_name_list $i]
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set prcfg_name_b [lindex $prcfg_name_list $j]
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pr_verify -full_check ./prcfg_${prcfg_name_a}/results/top_route_design.dcp \
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./prcfg_${prcfg_name_b}/results/top_route_design.dcp > \
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./verify_design/pr_verify_${counter}.rpt
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incr counter
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}
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}
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}
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# Generate bitstream
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proc prcfg_gen_bit { prcfg_name_list } {
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global part
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foreach i $prcfg_name_list {
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open_checkpoint "./prcfg_${i}/results/top_route_design.dcp" -part $part
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file mkdir "./prcfg_${i}/bit"
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write_bitstream -force -file "./prcfg_${i}/bit/config_${i}.bit"
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close_project
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}
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}
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