318 lines
11 KiB
Verilog
318 lines
11 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// This core supports pmods with AD7091R, it controls a simple three wire
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// SPI interface with an additional control line for conversion start
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// NOTE: The maximum clock rate is 100 Mhz, the SPI interface clock is always
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// half of the core's clock.
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`timescale 1ns/1ns
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module util_pmod_adc (
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// clock and reset signals
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clk,
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reset,
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// dma interface
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adc_data,
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adc_valid,
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adc_enable,
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adc_dbg,
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// adc interface (clk, data, cs and conversion start)
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adc_sdo,
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adc_sclk,
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adc_cs_n,
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adc_convst_n
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);
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// parameters and local parameters
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parameter real FPGA_CLOCK_FREQ = 100; // FPGA clock frequency [MHz] NOTE: this is the maximum supported frequency
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parameter real ADC_CYCLE_TIME = 1.000; // minimum time between two ADC conversions [us]
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parameter real ADC_CONVST_TIME = 0.010; // minimum time to keep /CONVST low [us]
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parameter real ADC_CONVERT_TIME = 0.650; // conversion time [us]
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parameter ADC_SCLK_PERIODS = 5'd12;
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parameter ADC_RESET_SCLK_PERIODS = 4'd3;
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// ADC states
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localparam ADC_SW_RESET_STATE = 8'b00000001;
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localparam ADC_IDLE_STATE = 8'b00000010;
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localparam ADC_START_CNV_STATE = 8'b00000100;
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localparam ADC_WAIT_CNV_DONE_STATE = 8'b00001000;
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localparam ADC_WAIT_DATA_VALID_STATE = 8'b00010000;
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localparam ADC_READ_CNV_RESULT = 8'b00100000;
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localparam ADC_END_CNV_STATE = 8'b01000000;
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localparam ADC_DATAREADY_STATE = 8'b10000000;
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// ADC timing
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localparam [6:0] ADC_CYCLE_CNT = FPGA_CLOCK_FREQ * ADC_CYCLE_TIME - 1;
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localparam [6:0] ADC_CONVST_CNT = FPGA_CLOCK_FREQ * ADC_CONVST_TIME - 1;
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localparam [6:0] ADC_CONVERT_CNT = FPGA_CLOCK_FREQ * ADC_CONVERT_TIME - 1;
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// clock and reset signals
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input clk; // system clock (100 MHz)
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input reset; // active high reset signal
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// dma interface
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output [15:0] adc_data;
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output adc_valid;
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output adc_enable;
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output [ 7:0] adc_dbg; // signals that the first data acquisition has been performed
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// adc interface
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input adc_sdo;
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output adc_sclk;
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output adc_cs_n;
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output adc_convst_n;
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reg [15:0] adc_data = 'd0;
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reg adc_valid = 'b0;
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reg adc_enable = 'b0;
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reg [ 7:0] adc_dbg = 'b0;
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reg adc_clk = 'd0;
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reg [ 7:0] adc_state = 'b0; // current state for the ADC control state machine
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reg [ 7:0] adc_next_state = 'b0; // next state for the ADC control state machine
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reg [ 7:0] adc_state_nc_m1 = 'b0; // current state for the ADC state machine in the ADC clock domain sampled on the falling edge
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reg [ 7:0] adc_state_pc_m1 = 'b0; // current state for the ADC state machine in the ADC clock domain sampled on the rising edge
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reg [ 6:0] adc_tcycle_cnt = 'b0;
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reg [ 6:0] adc_tconvst_cnt = 'b0;
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reg [ 6:0] adc_tconvert_cnt = 'b0;
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reg [ 4:0] sclk_clk_cnt = 'b0;
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reg adc_cnv_s = 'b0;
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reg adc_clk_en = 1'b0;
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reg adc_cs_n_s = 'b0;
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reg [15:0] adc_data_s = 'b0;
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reg adc_sw_reset = 'b0;
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reg data_rd_ready_s = 'b0;
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// Assign/Always Blocks
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assign adc_sclk = adc_clk & adc_clk_en;
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assign adc_cs_n = adc_cs_n_s;
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assign adc_convst_n = adc_cnv_s;
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always @(negedge clk) begin
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if(reset == 1'b1) begin
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adc_valid <= 1'b0;
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adc_enable <= 1'b0;
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end else begin
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adc_valid <= data_rd_ready_s;
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adc_enable <= 1'b1;
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if(adc_valid == 1'b1) begin
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adc_data <= adc_data_s;
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end
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end
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end
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// generate ADC clock, max rate is 50 Mhz
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always @(posedge clk) begin
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adc_clk<= ~adc_clk;
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end
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// update the ADC timing counters
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always @(posedge clk)
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begin
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if(reset == 1'b1) begin
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adc_tcycle_cnt <= 0;
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adc_tconvst_cnt <= ADC_CONVST_CNT;
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adc_tconvert_cnt <= ADC_CONVERT_CNT;
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end else begin
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if(adc_tcycle_cnt != 1'b0) begin
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adc_tcycle_cnt <= adc_tcycle_cnt - 7'h1;
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end
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else if(adc_state == ADC_IDLE_STATE || adc_state == ADC_SW_RESET_STATE) begin
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adc_tcycle_cnt <= ADC_CYCLE_CNT;
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end
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if(adc_state == ADC_START_CNV_STATE) begin
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adc_tconvst_cnt <= adc_tconvst_cnt - 7'h1;
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end
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else begin
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adc_tconvst_cnt <= ADC_CONVST_CNT;
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end
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if(adc_state == ADC_WAIT_CNV_DONE_STATE) begin
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adc_tconvert_cnt <= adc_tconvert_cnt - 7'h1;
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end
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else begin
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adc_tconvert_cnt <= ADC_CONVERT_CNT;
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end
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end
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end
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// determine when the ADC clock is valid to be sent to the ADC
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always @(negedge adc_clk) begin
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adc_state_nc_m1 <= adc_state;
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adc_clk_en <= ((adc_state_nc_m1 == ADC_WAIT_DATA_VALID_STATE) ||
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(adc_state_nc_m1 == ADC_READ_CNV_RESULT) &&
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((sclk_clk_cnt != 0) ||
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((adc_sw_reset == 1'b1) &&
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(sclk_clk_cnt == ADC_SCLK_PERIODS - ADC_RESET_SCLK_PERIODS)))) ? 1'b1 : 1'b0;
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end
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// read data from the ADC
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always @(negedge adc_clk) begin
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adc_state_pc_m1 <= adc_state;
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if(adc_clk_en == 1'b1) begin
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adc_data_s <= {3'b0, adc_data_s[11:0], adc_sdo};
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sclk_clk_cnt <= sclk_clk_cnt - 5'h1;
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end
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else if(adc_state_pc_m1 != ADC_READ_CNV_RESULT && adc_state_pc_m1 != ADC_END_CNV_STATE) begin
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adc_data_s <= 16'h0;
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sclk_clk_cnt <= ADC_SCLK_PERIODS - 1;
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end
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end
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// update the ADC current state and the control signals
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always @(posedge clk) begin
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if(reset == 1'b1) begin
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adc_state <= ADC_SW_RESET_STATE;
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adc_dbg <= 1'b0;
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end
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else begin
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adc_state <= adc_next_state;
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adc_dbg <= adc_state;
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case (adc_state)
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ADC_SW_RESET_STATE: begin
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adc_cnv_s <= 1'b1;
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adc_cs_n_s <= 1'b1;
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data_rd_ready_s <= 1'b0;
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adc_sw_reset <= 1'b1;
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end
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ADC_IDLE_STATE: begin
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adc_cnv_s <= 1'b1;
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adc_cs_n_s <= 1'b1;
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data_rd_ready_s <= 1'b0;
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adc_sw_reset <= 1'b0;
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end
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ADC_START_CNV_STATE: begin
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adc_cnv_s <= 1'b0;
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adc_cs_n_s <= 1'b1;
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data_rd_ready_s <= 1'b0;
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end
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ADC_WAIT_CNV_DONE_STATE: begin
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adc_cnv_s <= 1'b1;
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adc_cs_n_s <= 1'b1;
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data_rd_ready_s <= 1'b0;
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end
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ADC_WAIT_DATA_VALID_STATE: begin
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adc_cnv_s <= 1'b1;
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adc_cs_n_s <= 1'b1;
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data_rd_ready_s <= 1'b0;
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end
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ADC_READ_CNV_RESULT: begin
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adc_cnv_s <= 1'b1;
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adc_cs_n_s <= 1'b0;
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data_rd_ready_s <= 1'b0;
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end
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ADC_END_CNV_STATE: begin
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adc_cnv_s <= 1'b1;
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adc_cs_n_s <= 1'b0;
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data_rd_ready_s <= 1'b0;
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end
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ADC_DATAREADY_STATE: begin
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adc_cnv_s <= 1'b1;
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adc_cs_n_s <= 1'b0;
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data_rd_ready_s <= 1'b1;
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end
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endcase
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end
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end
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// update the ADC next state
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always @(adc_state, adc_tcycle_cnt, adc_tconvst_cnt, adc_tconvert_cnt, sclk_clk_cnt, adc_sw_reset) begin
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adc_next_state <= adc_state;
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case (adc_state)
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ADC_SW_RESET_STATE: begin
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adc_next_state <= ADC_START_CNV_STATE;
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end
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ADC_IDLE_STATE: begin
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if(adc_tcycle_cnt == 0) begin
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adc_next_state <= ADC_START_CNV_STATE;
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end
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end
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ADC_START_CNV_STATE: begin
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if(adc_tconvst_cnt == 0) begin
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adc_next_state <= ADC_WAIT_CNV_DONE_STATE;
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end
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end
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ADC_WAIT_CNV_DONE_STATE: begin
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if(adc_tconvert_cnt == 0) begin
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adc_next_state <= ADC_WAIT_DATA_VALID_STATE;
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end
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end
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ADC_WAIT_DATA_VALID_STATE: begin
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adc_next_state <= ADC_READ_CNV_RESULT;
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end
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ADC_READ_CNV_RESULT: begin
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if((sclk_clk_cnt == 0) || ((adc_sw_reset == 1'b1) && (sclk_clk_cnt == ADC_SCLK_PERIODS - ADC_RESET_SCLK_PERIODS))) begin
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adc_next_state <= ADC_END_CNV_STATE;
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end
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end
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ADC_END_CNV_STATE: begin
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adc_next_state <= ADC_DATAREADY_STATE;
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end
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ADC_DATAREADY_STATE: begin
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adc_next_state <= ADC_IDLE_STATE;
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end
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default: begin
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adc_next_state <= ADC_IDLE_STATE;
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end
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endcase
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end
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endmodule
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