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Iulia Moldovan 961ebe0cc2 projects: Update .v files according to guideline 
Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
 		2022-06-28 18:06:56 +03:00
..
Makefile Adaq8092 on ZedBoard LVDS output mode (#921) 2022-04-28 15:39:59 +03:00
system_bd.tcl Adaq8092 on ZedBoard LVDS output mode (#921) 2022-04-28 15:39:59 +03:00
system_constr.xdc Adaq8092 on ZedBoard LVDS output mode (#921) 2022-04-28 15:39:59 +03:00
system_project.tcl Adaq8092 on ZedBoard LVDS output mode (#921) 2022-04-28 15:39:59 +03:00
system_top.v projects: Update .v files according to guideline 2022-06-28 18:06:56 +03:00