Istvan Csomortani c926daca3a ad9361/tdd: Fix generation of tx_valid_* signals ... In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals. In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.		2015-06-08 16:22:21 +03:00
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Makefile	Makefiles: Updated makefiles to have as a result the programming file instead of the project file.	2015-05-18 17:22:46 +03:00
axi_ad9361.v	ad9361/tdd: Fix generation of tx_valid_* signals	2015-06-08 16:22:21 +03:00
axi_ad9361_alt_lvds_rx.v	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
axi_ad9361_alt_lvds_tx.v	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
axi_ad9361_constr.xdc	axi_ad9361: Add ASYNC_REG properties to CDC regs and add missing -datapath_only	2015-04-21 10:15:02 +02:00
axi_ad9361_dev_if.v	delay-cntrl: up-clk, direct access + tx	2015-05-18 14:28:20 -04:00
axi_ad9361_dev_if_alt.v	delay-cntrl: up-clk, direct access + tx	2015-05-18 14:28:20 -04:00
axi_ad9361_hw.tcl	ad_rst- non lpm version	2015-06-04 10:53:12 -04:00
axi_ad9361_ip.tcl	ad9361: ip defaults & rst output	2015-06-05 09:19:39 -04:00
axi_ad9361_rx.v	library- drp moved to up-clock domain	2015-06-01 14:52:52 -04:00
axi_ad9361_rx_channel.v	up/constr: independent read/write and local constraints	2014-10-02 14:35:59 -04:00
axi_ad9361_rx_pnmon.v	Remove executable flags from non-exectuable files	2014-09-09 15:05:06 +02:00
axi_ad9361_tdd.v	ad9361/tdd: Fix generation of tx_valid_* signals	2015-06-08 16:22:21 +03:00
axi_ad9361_tdd_if.v	axi_ad9361/tdd: Cherry picked commit 598ece4 from hdl_2015_r1 branch	2015-06-04 18:09:47 +03:00
axi_ad9361_tx.v	library- drp moved to up-clock domain	2015-06-01 14:52:52 -04:00
axi_ad9361_tx_channel.v	up/constr: independent read/write and local constraints	2014-10-02 14:35:59 -04:00