150 lines
4.1 KiB
Verilog
150 lines
4.1 KiB
Verilog
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//-----------------------------------------------------------------
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//
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// Filename : synth_reg.v
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//
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// Date : 4/19/2005
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//
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// Description : Verilog description of SRL16E based delay and
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// retiming register module.
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// This code is synthesizable.
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//
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//
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// Mod. History : Translated VHDL code to Verilog
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// : Fixed synth_reg_reg
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//
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// Mod. Dates : 6/29/2004
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// : 12/14/2004
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//
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//-------------------------------------------------------------------
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`timescale 1 ns / 10 ps
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module srl17e (clk, ce, d, q);
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parameter width = 16;
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parameter latency = 8;
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input clk, ce;
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input [width-1:0] d;
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output [width-1:0] q;
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parameter signed [5:0] a = latency - 2;
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wire[width - 1:0] #0.2 d_delayed;
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wire[width - 1:0] srl16_out;
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genvar i;
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assign d_delayed = d ;
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generate
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for(i=0; i<width; i=i+1)
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begin:reg_array
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if (latency > 1)
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begin: has_2_latency
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SRL16E u1 (.CLK(clk), .D(d_delayed[i]), .Q(srl16_out[i]), .CE(ce), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]));
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end
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if (latency <= 1)
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begin: has_1_latency
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assign srl16_out[i] = d_delayed[i];
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end
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if (latency != 0)
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begin: has_latency
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FDE u2 (.C(clk), .D(srl16_out[i]), .Q(q[i]), .CE(ce));
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end
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if (latency == 0)
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begin:has_0_latency
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assign q[i] = srl16_out[i];
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end
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end
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endgenerate
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endmodule
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module synth_reg (i, ce, clr, clk, o);
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parameter width = 8;
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parameter latency = 1;
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input[width - 1:0] i;
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input ce,clr,clk;
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output[width - 1:0] o;
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parameter complete_num_srl17es = latency/17;
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parameter remaining_latency = latency%17;
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parameter temp_num_srl17es = (latency/17) + ((latency%17)?1:0);
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parameter num_srl17es = temp_num_srl17es ? temp_num_srl17es : 1;
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wire [width - 1:0] z [0:num_srl17es-1];
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genvar t;
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generate
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if (latency <= 17)
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begin:has_only_1
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srl17e #(width, latency) srl17e_array0(.clk(clk), .ce(ce), .d(i), .q(o));
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end
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endgenerate
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generate
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if (latency > 17)
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begin:has_1
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assign o = z[num_srl17es-1];
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srl17e #(width, 17) srl17e_array0(.clk(clk), .ce(ce), .d(i), .q(z[0]));
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end
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endgenerate
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generate
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if (latency > 17)
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begin:more_than_1
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for (t=1; t < complete_num_srl17es; t=t+1)
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begin:left_complete_ones
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srl17e #(width, 17) srl17e_array(.clk(clk), .ce(ce), .d(z[t-1]), .q(z[t]));
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end
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end
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endgenerate
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generate
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if ((remaining_latency > 0) && (latency>17))
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begin:remaining_ones
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srl17e #(width, (latency%17)) last_srl17e (.clk(clk), .ce(ce), .d(z[num_srl17es-2]), .q(z[num_srl17es-1]));
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end
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endgenerate
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endmodule
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module synth_reg_reg (i, ce, clr, clk, o);
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parameter width = 8;
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parameter latency = 1;
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input[width - 1:0] i;
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input ce, clr, clk;
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output[width - 1:0] o;
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wire[width - 1:0] o;
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genvar idx;
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reg[width - 1:0] reg_bank [latency:0];
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integer j;
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initial
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begin
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for (j=0; j < latency+1; j=j+1)
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begin
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reg_bank[j] = {width{1'b0}};
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end
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end
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generate
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if (latency == 0)
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begin:has_0_latency
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assign o = i;
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end
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endgenerate
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always @(i)
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begin
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reg_bank[0] = i;
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end
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generate
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if (latency > 0)
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begin:more_than_1
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assign o = reg_bank[latency];
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for (idx=0; idx < latency; idx=idx+1) begin:sync_loop
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always @(posedge clk)
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begin
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if(clr)
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begin
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//for (j=0; j < latency+1; j=j+1)
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// begin
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reg_bank[idx+1] = {width{1'b0}};
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// end
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end
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else if (ce)
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begin
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reg_bank[idx+1] <= reg_bank[idx] ;
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end
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end
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end
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end
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endgenerate
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endmodule
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