164 lines
4.1 KiB
Verilog
164 lines
4.1 KiB
Verilog
// -------------------------------------------------------------
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//
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// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\PWM.v
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// Created: 2014-09-08 14:12:09
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//
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// Generated by MATLAB 8.2 and HDL Coder 3.3
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//
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// -------------------------------------------------------------
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// -------------------------------------------------------------
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//
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// Module: PWM
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// Source Path: controllerPeripheralHdlAdi/PWM
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// Hierarchy Level: 1
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//
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// -------------------------------------------------------------
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`timescale 1 ns / 1 ns
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module PWM
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(
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CLK_IN,
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reset,
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enb,
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c_0,
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c_1,
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c_2,
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pwm_0,
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pwm_1,
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pwm_2
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);
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input CLK_IN;
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input reset;
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input enb;
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input [15:0] c_0; // uint16
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input [15:0] c_1; // uint16
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input [15:0] c_2; // uint16
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output pwm_0; // boolean
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output pwm_1; // boolean
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output pwm_2; // boolean
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wire [15:0] Timer_Period_Clock_Cycles_out1; // uint16
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wire [15:0] Chart_out1; // uint16
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wire [15:0] c [0:2]; // uint16 [3]
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wire [15:0] Add_out1 [0:2]; // uint16 [3]
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wire [15:0] Add_out1_0; // uint16
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wire Relational_Operator_relop1;
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wire [15:0] Add_out1_1; // uint16
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wire Relational_Operator_relop2;
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wire [15:0] Add_out1_2; // uint16
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wire Relational_Operator_relop3;
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wire [0:2] Relational_Operator_out1; // boolean [3]
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wire Relational_Operator_out1_0;
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wire [0:2] Compare_To_Zero_out1; // boolean [3]
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wire Compare_To_Zero_out1_0;
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wire Relational_Operator_out1_0_1;
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wire Relational_Operator_out1_1;
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wire Compare_To_Zero_out1_1;
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wire Relational_Operator_out1_1_1;
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wire Relational_Operator_out1_2;
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wire Compare_To_Zero_out1_2;
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wire Relational_Operator_out1_2_1;
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// <S2>/Timer Period Clock Cycles
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assign Timer_Period_Clock_Cycles_out1 = 16'd1000;
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// <S2>/Chart
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Chart u_Chart (.CLK_IN(CLK_IN),
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.reset(reset),
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.enb(enb),
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.CounterMax(Timer_Period_Clock_Cycles_out1), // uint16
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.count(Chart_out1) // uint16
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);
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assign c[0] = c_0;
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assign c[1] = c_1;
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assign c[2] = c_2;
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// <S2>/Add
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assign Add_out1[0] = Timer_Period_Clock_Cycles_out1 - c[0];
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assign Add_out1[1] = Timer_Period_Clock_Cycles_out1 - c[1];
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assign Add_out1[2] = Timer_Period_Clock_Cycles_out1 - c[2];
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assign Add_out1_0 = Add_out1[0];
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assign Relational_Operator_relop1 = (Chart_out1 >= Add_out1_0 ? 1'b1 :
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1'b0);
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assign Add_out1_1 = Add_out1[1];
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assign Relational_Operator_relop2 = (Chart_out1 >= Add_out1_1 ? 1'b1 :
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1'b0);
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assign Add_out1_2 = Add_out1[2];
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// <S2>/Relational Operator
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assign Relational_Operator_relop3 = (Chart_out1 >= Add_out1_2 ? 1'b1 :
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1'b0);
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assign Relational_Operator_out1[0] = Relational_Operator_relop1;
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assign Relational_Operator_out1[1] = Relational_Operator_relop2;
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assign Relational_Operator_out1[2] = Relational_Operator_relop3;
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assign Relational_Operator_out1_0 = Relational_Operator_out1[0];
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// <S2>/Compare To Zero
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assign Compare_To_Zero_out1[0] = (c[0] != 16'b0000000000000000 ? 1'b1 :
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1'b0);
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assign Compare_To_Zero_out1[1] = (c[1] != 16'b0000000000000000 ? 1'b1 :
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1'b0);
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assign Compare_To_Zero_out1[2] = (c[2] != 16'b0000000000000000 ? 1'b1 :
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1'b0);
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assign Compare_To_Zero_out1_0 = Compare_To_Zero_out1[0];
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assign Relational_Operator_out1_0_1 = Relational_Operator_out1_0 & Compare_To_Zero_out1_0;
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assign pwm_0 = Relational_Operator_out1_0_1;
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assign Relational_Operator_out1_1 = Relational_Operator_out1[1];
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assign Compare_To_Zero_out1_1 = Compare_To_Zero_out1[1];
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assign Relational_Operator_out1_1_1 = Relational_Operator_out1_1 & Compare_To_Zero_out1_1;
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assign pwm_1 = Relational_Operator_out1_1_1;
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assign Relational_Operator_out1_2 = Relational_Operator_out1[2];
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assign Compare_To_Zero_out1_2 = Compare_To_Zero_out1[2];
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// <S2>/Logical Operator
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assign Relational_Operator_out1_2_1 = Relational_Operator_out1_2 & Compare_To_Zero_out1_2;
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assign pwm_2 = Relational_Operator_out1_2_1;
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endmodule // PWM
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