286 lines
8.4 KiB
VHDL
286 lines
8.4 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2013(c) Analog Devices, Inc.
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-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
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--
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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-- - Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- - Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in
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-- the documentation and/or other materials provided with the
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-- distribution.
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-- - Neither the name of Analog Devices, Inc. nor the names of its
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-- contributors may be used to endorse or promote products derived
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-- from this software without specific prior written permission.
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-- - The use of this software may or may not infringe the patent rights
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-- of one or more patent holders. This license does not release you
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-- from the requirement that you obtain separate licenses from these
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-- patent holders to use this software.
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-- - Use of the software either in source or binary form, must be run
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-- on or directly connected to an Analog Devices Inc. component.
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--
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-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED.
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--
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-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.fifo_synchronizer;
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use work.i2s_clkgen;
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use work.i2s_tx;
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use work.i2s_rx;
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entity i2s_controller is
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generic(
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C_SLOT_WIDTH : integer := 24; -- Width of one Slot
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C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
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C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
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C_NUM_CH : integer := 1;
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C_HAS_TX : integer := 1;
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C_HAS_RX : integer := 1
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);
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port(
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clk : in std_logic; -- System clock
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resetn : in std_logic; -- System reset
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data_clk : in std_logic; -- Data clock should be less than clk / 4
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BCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Bit Clock
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LRCLK_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Frame Clock
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SDATA_O : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Output
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SDATA_I : in std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Input
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tx_enable : in Boolean; -- Enable TX
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tx_ack : out std_logic; -- Request new Slot Data
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tx_stb : in std_logic; -- Request new Slot Data
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tx_data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in
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rx_enable : in Boolean; -- Enable RX
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rx_ack : in std_logic;
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rx_stb : out std_logic; -- Valid Slot Data
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rx_data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out
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-- Runtime parameter
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bclk_div_rate : in natural range 0 to 255;
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lrclk_div_rate : in natural range 0 to 255
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);
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end i2s_controller;
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architecture Behavioral of i2s_controller is
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constant NUM_TX : integer := C_HAS_TX * C_NUM_CH;
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constant NUM_RX : integer := C_HAS_RX * C_NUM_CH;
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signal enable : Boolean;
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signal tick : std_logic;
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signal tick_d1 : std_logic;
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signal tick_d2 : std_logic;
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signal BCLK_O_int : std_logic;
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signal LRCLK_O_int : std_logic;
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signal tx_bclk : std_logic;
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signal tx_lrclk : std_logic;
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signal tx_sdata : std_logic_vector(C_NUM_CH - 1 downto 0);
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signal tx_tick : std_logic;
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signal tx_channel_sync : std_logic;
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signal tx_frame_sync : std_logic;
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signal const_1 : std_logic;
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signal bclk_tick : std_logic;
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signal rx_bclk : std_logic;
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signal rx_lrclk : std_logic;
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signal rx_sdata : std_logic_vector(NUM_RX - 1 downto 0);
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signal rx_channel_sync : std_logic;
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signal rx_frame_sync : std_logic;
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signal tx_sync_fifo_out : std_logic_vector(3 + NUM_TX downto 0);
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signal tx_sync_fifo_in : std_logic_vector(3 + NUM_TX downto 0);
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signal rx_sync_fifo_out : std_logic_vector(3 + NUM_RX downto 0);
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signal rx_sync_fifo_in : std_logic_vector(3 + NUM_RX downto 0);
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begin
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enable <= rx_enable or tx_enable;
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const_1 <= '1';
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-- Generate tick signal in the DATA_CLK_I domain
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process (data_clk)
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begin
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if rising_edge(data_clk) then
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if resetn = '0' then
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tick <= '0';
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else
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tick <= not tick;
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end if;
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end if;
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end process;
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process (clk)
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begin
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if rising_edge(clk) then
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if resetn = '0' then
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tick_d1 <= '0';
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tick_d2 <= '0';
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else
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tick_d1 <= tick;
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tick_d2 <= tick_d1;
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end if;
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end if;
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end process;
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tx_tick <= tick_d2 xor tick_d1;
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tx_sync_fifo_in(0) <= tx_channel_sync;
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tx_sync_fifo_in(1) <= tx_frame_sync;
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tx_sync_fifo_in(2) <= tx_bclk;
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tx_sync_fifo_in(3) <= tx_lrclk;
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tx_sync_fifo_in(3 + NUM_TX downto 4) <= tx_sdata;
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process (data_clk)
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begin
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if rising_edge(data_clk) then
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if resetn = '0' then
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BCLK_O <= (others => '1');
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LRCLK_O <= (others => '1');
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SDATA_O <= (others => '0');
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else
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if C_BCLK_POL = 0 then
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BCLK_O <= (others => tx_sync_fifo_out(2));
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else
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BCLK_O <= (others => not tx_sync_fifo_out(2));
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end if;
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if C_LRCLK_POL = 0 then
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LRCLK_O <= (others => tx_sync_fifo_out(3));
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else
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LRCLK_O <= (others => not tx_sync_fifo_out(3));
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end if;
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if C_HAS_TX = 1 then
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SDATA_O <= tx_sync_fifo_out(3 + NUM_TX downto 4);
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end if;
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if C_HAS_RX = 1 then
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rx_sync_fifo_in(3 downto 0) <= tx_sync_fifo_out(3 downto 0);
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rx_sync_fifo_in(3 + NUM_RX downto 4) <= SDATA_I;
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end if;
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end if;
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end if;
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end process;
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tx_sync: entity fifo_synchronizer
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generic map (
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DEPTH => 4,
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WIDTH => NUM_TX + 4
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)
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port map (
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resetn => resetn,
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in_clk => clk,
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in_data => tx_sync_fifo_in,
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in_tick => tx_tick,
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out_clk => data_clk,
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out_data => tx_sync_fifo_out
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);
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clkgen: entity i2s_clkgen
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port map(
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clk => clk,
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resetn => resetn,
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enable => enable,
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tick => tx_tick,
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bclk_div_rate => bclk_div_rate,
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lrclk_div_rate => lrclk_div_rate,
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channel_sync => tx_channel_sync,
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frame_sync => tx_frame_sync,
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bclk => tx_bclk,
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lrclk => tx_lrclk
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);
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tx_gen: if C_HAS_TX = 1 generate
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tx: entity i2s_tx
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generic map (
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C_SLOT_WIDTH => C_SLOT_WIDTH,
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C_NUM => NUM_TX
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)
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port map (
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clk => clk,
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resetn => resetn,
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enable => tx_enable,
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channel_sync => tx_channel_sync,
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frame_sync => tx_frame_sync,
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bclk => tx_bclk,
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sdata => tx_sdata,
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ack => tx_ack,
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stb => tx_stb,
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data => tx_data
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);
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end generate;
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rx_gen: if C_HAS_RX = 1 generate
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rx: entity i2s_rx
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generic map (
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C_SLOT_WIDTH => C_SLOT_WIDTH,
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C_NUM => NUM_RX
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)
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port map (
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clk => clk,
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resetn => resetn,
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enable => rx_enable,
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channel_sync => rx_channel_sync,
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frame_sync => rx_frame_sync,
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bclk => rx_bclk,
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sdata => rx_sdata,
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ack => rx_ack,
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stb => rx_stb,
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data => rx_data
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);
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rx_channel_sync <= rx_sync_fifo_out(0);
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rx_frame_sync <= rx_sync_fifo_out(1);
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rx_bclk <= rx_sync_fifo_out(2);
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rx_lrclk <= rx_sync_fifo_out(3);
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rx_sdata <= rx_sync_fifo_out(3 + NUM_RX downto 4);
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rx_sync: entity fifo_synchronizer
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generic map (
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DEPTH => 4,
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WIDTH => NUM_RX + 4
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)
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port map (
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resetn => resetn,
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in_clk => data_clk,
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in_data => rx_sync_fifo_in,
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in_tick => const_1,
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out_clk => clk,
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out_data => rx_sync_fifo_out
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);
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end generate;
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end Behavioral;
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