960883c789
The dac_xfer_req should indicate one single thing, that the FIFO is in read phase. Should not be affected by any signals, which indicates data validity on any interface. (e.g. dac_valid) This signal is not used by the device core, its main purpose is to indicate the state of the interface for a posible intermediat processing module. |
||
---|---|---|
library | ||
projects | ||
.gitattributes | ||
.gitignore | ||
LICENSE | ||
LICENSE_ADIBSD | ||
LICENSE_GPL2 | ||
LICENSE_LGPL | ||
Makefile | ||
README.md |
README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects
Branches
Each release has its own branch and master always synced with the latest release. To find out more information about the latest release please check the release notes. Every branch, which has dev in its name, is a development branch and should handle it accordingly.