Lars-Peter Clausen 95a46bf1e1 pzsdr1/pzsdr2: audio_clkgen: Disable phase alignment ... There is no need for the audio clock to be phase aligned to its source clock. When phase alignment is disabled the MMCM uses an internal feedback path without requiring external resources, so disable it. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-04-21 13:22:33 +02:00
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ccbox_bd.tcl	pzsdr1/pzsdr2: audio_clkgen: Disable phase alignment	2017-04-21 13:22:33 +02:00
ccbox_constr.xdc	pzsdr1/pzsdr2- ccbox added tws	2017-04-18 11:37:23 -04:00
ccbrk_bd.tcl	pzsdr1/common- updates	2016-11-17 15:31:25 -05:00
ccbrk_constr.xdc	pzsdr1/common- updates	2016-11-17 15:31:25 -05:00
ccusb_bd.tcl	pzsdr1: ccusb, connect unused clock pins to GND	2017-02-14 11:50:37 +02:00
ccusb_constr.xdc	pzsdr1: ccusb_lvds, add flag_a,flag_b signals	2016-11-30 17:38:04 +02:00
pzsdr1_bd.tcl	pzsdr1: Don't set a disabled parameter	2017-02-14 11:50:06 +02:00
pzsdr1_constr.xdc	pzsdr1- common files	2016-11-17 13:40:04 -05:00
pzsdr1_constr_cmos.xdc	pzsdr1- common files	2016-11-17 13:40:04 -05:00
pzsdr1_constr_lvds.xdc	pzsdr1/lvds: The interface runs at max 122.88 MHz	2016-12-09 11:45:11 +02:00