71 lines
2.7 KiB
Tcl
71 lines
2.7 KiB
Tcl
###############################################################################
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## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 adaq7980_spi
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source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
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set data_width 16
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set async_spi_clk 1
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set num_cs 1
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set num_sdi 1
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set num_sdo 1
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set sdi_delay 1
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set echo_sclk 0
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set hier_spi_engine spi_adaq7980_adc
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spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
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# axi_pwm_gen
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ad_ip_instance axi_pwm_gen spi_trigger_gen
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ad_ip_parameter spi_trigger_gen CONFIG.PULSE_0_PERIOD 160
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ad_ip_parameter spi_trigger_gen CONFIG.PULSE_0_WIDTH 1
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ad_ip_instance axi_dmac axi_adaq7980_dma
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ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adaq7980_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adaq7980_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_adaq7980_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_adaq7980_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_DATA_WIDTH_SRC 16
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ad_ip_parameter axi_adaq7980_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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# axi_clkgen
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ad_ip_instance axi_clkgen spi_clkgen
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ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5
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ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1
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ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
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ad_connect $sys_cpu_clk spi_clkgen/clk
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ad_connect spi_clk spi_clkgen/clk_0
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ad_connect spi_clk spi_trigger_gen/ext_clk
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ad_connect $sys_cpu_clk spi_trigger_gen/s_axi_aclk
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ad_connect sys_cpu_resetn spi_trigger_gen/s_axi_aresetn
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ad_connect spi_trigger_gen/pwm_0 $hier_spi_engine/trigger
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ad_connect axi_adaq7980_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE
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ad_connect $hier_spi_engine/m_spi adaq7980_spi
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ad_connect $sys_cpu_clk $hier_spi_engine/clk
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ad_connect spi_clk $hier_spi_engine/spi_clk
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ad_connect spi_clk axi_adaq7980_dma/s_axis_aclk
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ad_connect sys_cpu_resetn $hier_spi_engine/resetn
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ad_connect sys_cpu_resetn axi_adaq7980_dma/m_dest_axi_aresetn
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ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
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ad_cpu_interconnect 0x44a30000 axi_adaq7980_dma
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ad_cpu_interconnect 0x44a70000 spi_clkgen
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ad_cpu_interconnect 0x44b00000 spi_trigger_gen
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ad_cpu_interrupt "ps-13" "mb-13" axi_adaq7980_dma/irq
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ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
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ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect sys_cpu_clk axi_adaq7980_dma/m_dest_axi
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