Adrian Costina 9364c8501a adrv9009_zu11eg: Add synchronization at application layer ... Switch RX path reset to be controlled by the TPL and use RX SYSREF as external synchronization for the ADC TPL Use TX SYSREF for synchornizing the TX DDS		2020-10-07 09:04:21 +03:00
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adrv2crr_fmc_bd.tcl	axi_fan_control: Changed temperature thresholds to registers	2020-02-14 11:21:12 +02:00
adrv2crr_fmc_constr.xdc	adrv9009zu11eg: Extend SPI connection to the PL HD PINS expansion	2020-02-18 11:19:02 +02:00
adrv9009zu11eg_bd.tcl	adrv9009_zu11eg: Add synchronization at application layer	2020-10-07 09:04:21 +03:00
adrv9009zu11eg_constr.xdc	adrv9009zu11eg: Reduce SPI Clock speed to meet timing	2019-11-19 10:29:57 +02:00
adrv9009zu11eg_spi.v	adrv9009_zu11eg_som: Change design partitioning	2019-11-14 15:25:23 +02:00