122 lines
3.9 KiB
Verilog
122 lines
3.9 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module elastic_buffer #(
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parameter IWIDTH = 32,
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parameter OWIDTH = 48,
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parameter SIZE = 256,
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parameter ASYNC_CLK = 0
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) (
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input clk,
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input reset,
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input device_clk,
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input device_reset,
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input [IWIDTH-1:0] wr_data,
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output reg [OWIDTH-1:0] rd_data,
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input ready_n,
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input do_release_n
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);
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localparam ADDR_WIDTH = SIZE > 128 ? 7 :
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SIZE > 64 ? 6 :
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SIZE > 32 ? 5 :
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SIZE > 16 ? 4 :
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SIZE > 8 ? 3 :
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SIZE > 4 ? 2 :
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SIZE > 2 ? 1 : 0;
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localparam WIDTH = OWIDTH >= IWIDTH ? OWIDTH : IWIDTH;
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reg [ADDR_WIDTH:0] wr_addr = 'h00;
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reg [ADDR_WIDTH:0] rd_addr = 'h00;
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(* ram_style = "distributed" *) reg [WIDTH-1:0] mem[0:SIZE - 1];
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wire mem_wr;
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wire [WIDTH-1:0] mem_wr_data;
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generate if ((OWIDTH > IWIDTH) && ASYNC_CLK) begin
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ad_pack #(
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.I_W(IWIDTH/8),
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.O_W(OWIDTH/8),
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.UNIT_W(8)
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) i_ad_pack (
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.clk(clk),
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.reset(ready_n),
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.idata(wr_data),
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.ivalid(1'b1),
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.odata(mem_wr_data),
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.ovalid(mem_wr));
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end else begin
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assign mem_wr = 1'b1;
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assign mem_wr_data = wr_data;
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end
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endgenerate
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always @(posedge clk) begin
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if (ready_n == 1'b1) begin
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wr_addr <= 'h00;
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end else if (mem_wr) begin
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mem[wr_addr] <= mem_wr_data;
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wr_addr <= wr_addr + 1'b1;
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end
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end
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always @(posedge device_clk) begin
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if (do_release_n == 1'b1) begin
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rd_addr <= 'h00;
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end else begin
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rd_addr <= rd_addr + 1'b1;
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rd_data <= mem[rd_addr];
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end
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end
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endmodule
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