.. |
bd
|
jesd204: Xilinx: NP=12 support
|
2021-02-05 15:24:15 +02:00 |
Makefile
|
jesd204_rx: fixed makefile
|
2021-10-07 12:48:08 +03:00 |
align_mux.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
elastic_buffer.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
error_monitor.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
jesd204_ilas_monitor.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
jesd204_lane_latency_monitor.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
jesd204_rx.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
jesd204_rx_cgs.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
jesd204_rx_constr.sdc
|
jesd204: Intel: NP12 support
|
2021-02-05 15:24:15 +02:00 |
jesd204_rx_constr.ttcl
|
jesd204_rx_constr.ttcl: Remove ASYNC_REG constraint from i_lmfc/cdc_sync_stage1_reg
|
2021-03-22 10:55:00 +02:00 |
jesd204_rx_ctrl.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
jesd204_rx_ctrl_64b.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
jesd204_rx_frame_align.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
jesd204_rx_header.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
jesd204_rx_hw.tcl
|
library/jesd204: Updated jesd to support more lanes
|
2022-08-04 13:10:53 +03:00 |
jesd204_rx_ip.tcl
|
library/jesd204: Updated jesd to support more lanes
|
2022-08-04 13:10:53 +03:00 |
jesd204_rx_lane.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
jesd204_rx_lane_64b.v
|
libraries: Update modules according to guideline
|
2022-06-28 18:06:56 +03:00 |
jesd204_rx_ooc.ttcl
|
jesd204: Add out of context constraint file for link layer cores
|
2021-05-14 15:39:40 +03:00 |