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Lars-Peter Clausen 91bb54467b axi_dmac: Generate per core instance constraint file 
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.

This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.

This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2015-09-18 15:27:12 +02:00
..
axi_ad6676 Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_ad9122 axi_ad9122: Updated core with latest constraints 2015-09-16 15:48:33 +03:00
axi_ad9144 Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_ad9152 Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_ad9234 Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_ad9250 Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_ad9265 axi_ad9265: Updated core with latest constraints 2015-09-11 11:26:28 +03:00
axi_ad9361 Makefiles: Update Make 2015-09-09 17:13:19 +03:00
axi_ad9434 Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_ad9467 Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_ad9625 Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_ad9643 axi_ad9643: Updated core with latest constraints 2015-09-16 15:49:13 +03:00
axi_ad9652 Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_ad9671 Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_ad9680 Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_ad9739a axi_ad9739a: Updated core with latest constraints 2015-09-11 14:04:33 +03:00
axi_adcfifo Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_clkgen Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_dmac axi_dmac: Generate per core instance constraint file 2015-09-18 15:27:12 +02:00
axi_generic_adc Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_hdmi_rx Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_hdmi_tx Makefiles: Update Make 2015-09-09 17:13:19 +03:00
axi_i2s_adi Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_jesd_gt Makefiles: Update Make 2015-09-09 17:13:19 +03:00
axi_jesd_xcvr xcvr- remove status constraint 2015-08-20 13:54:15 -04:00
axi_mc_controller Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_mc_current_monitor Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_mc_speed Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_spdif_rx Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
axi_spdif_tx Revert commit 6b99ce 2015-08-26 13:48:28 +03:00
cn0363 Add CN0363 project 2015-05-21 17:21:35 +02:00
common common library: Registered dc_filter and iq_correction coefficients 2015-09-16 14:24:18 +03:00
cordic_demod Add cordic demodulator module 2015-05-21 17:21:35 +02:00
interfaces interfaces-- transceiver cores 2015-08-14 15:33:36 -04:00
prcfg Add .gitattributes file 2015-07-01 18:43:51 +02:00
scripts adi_ip.tcl: Add helper function to add TTCL files to a core 2015-09-18 15:27:10 +02:00
spi_engine library: 2015.2 updates 2015-08-25 09:13:24 +03:00
util_adc_pack hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
util_adcfifo hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
util_axis_fifo util_axis_fifo: Fix port names at util_axis_fifo_ip.tcl 2015-08-25 09:41:34 +03:00
util_axis_resize hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
util_bsplit hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
util_ccat hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
util_cpack xpack- remove useless interfaces 2015-08-26 14:12:14 -04:00
util_dac_unpack hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
util_dacfifo dacfifo- remove interfaces 2015-08-27 11:18:00 -04:00
util_gmii_to_rgmii library: 2015.2 updates 2015-08-25 09:13:24 +03:00
util_gtlb gtlb- remove pn test-reset 2015-09-08 13:52:33 -04:00
util_i2c_mixer Add .gitattributes file 2015-07-01 18:43:51 +02:00
util_jesd_gt Makefiles: Update Make 2015-09-09 17:13:19 +03:00
util_pmod_adc Add .gitattributes file 2015-07-01 18:43:51 +02:00
util_pmod_fmeter hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
util_rfifo hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
util_sigma_delta_spi hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
util_upack xpack- remove useless interfaces 2015-08-26 14:12:14 -04:00
util_wfifo util_wfifo: Changed some reset for several registers from asynchronous to synchronous for better integration with the FIFO 2015-09-16 18:55:47 +03:00
Makefile Makefiles: Update Make 2015-09-09 17:13:19 +03:00