Go to file
Lars-Peter Clausen 91782989ad pzsdr: ccpci: Set IO standard to LVCMOS33 for banks 12 and 13
The IO voltage for bank 12 and 13 is 3.3V on the PCIe carrier. Set the
IOSTANDARD of the pins on these banks accordingly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
library cleanup: Don't need Makefiles specific to xilinx/altera libraries. Top Makefile covers them 2016-08-05 16:27:52 +03:00
projects pzsdr: ccpci: Set IO standard to LVCMOS33 for banks 12 and 13 2016-08-05 18:31:40 +02:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore file 2016-03-16 09:18:49 +02:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

README.md

HDL Reference Designs

Analog Devices Inc. HDL libraries and projects

Branches

Each release has its own branch and master always synced with the latest release. To find out more information about the latest release please check the release notes. Every branch, which has dev in its name, is a development branch and should handle it accordingly.

Latest Release Notes

HDL User Guide

HDL Help & Support