835 lines
23 KiB
Verilog
835 lines
23 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module ad_tdd_control#(
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parameter integer TX_DATA_PATH_DELAY = 0,
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parameter integer CONTROL_PATH_DELAY = 0) (
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// clock and reset
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input clk,
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input rst,
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// TDD timing signals
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input tdd_enable,
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input tdd_secondary,
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input tdd_tx_only,
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input tdd_rx_only,
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input [ 7:0] tdd_burst_count,
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input [23:0] tdd_counter_init,
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input [23:0] tdd_frame_length,
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input [23:0] tdd_vco_rx_on_1,
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input [23:0] tdd_vco_rx_off_1,
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input [23:0] tdd_vco_tx_on_1,
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input [23:0] tdd_vco_tx_off_1,
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input [23:0] tdd_rx_on_1,
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input [23:0] tdd_rx_off_1,
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input [23:0] tdd_rx_dp_on_1,
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input [23:0] tdd_rx_dp_off_1,
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input [23:0] tdd_tx_on_1,
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input [23:0] tdd_tx_off_1,
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input [23:0] tdd_tx_dp_on_1,
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input [23:0] tdd_tx_dp_off_1,
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input [23:0] tdd_vco_rx_on_2,
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input [23:0] tdd_vco_rx_off_2,
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input [23:0] tdd_vco_tx_on_2,
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input [23:0] tdd_vco_tx_off_2,
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input [23:0] tdd_rx_on_2,
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input [23:0] tdd_rx_off_2,
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input [23:0] tdd_rx_dp_on_2,
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input [23:0] tdd_rx_dp_off_2,
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input [23:0] tdd_tx_on_2,
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input [23:0] tdd_tx_off_2,
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input [23:0] tdd_tx_dp_on_2,
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input [23:0] tdd_tx_dp_off_2,
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input tdd_sync,
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// TDD control signals
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output reg tdd_tx_dp_en,
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output reg tdd_rx_dp_en,
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output reg tdd_rx_vco_en,
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output reg tdd_tx_vco_en,
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output reg tdd_rx_rf_en,
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output reg tdd_tx_rf_en,
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output [23:0] tdd_counter_status);
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localparam [ 0:0] ON = 1;
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localparam [ 0:0] OFF = 0;
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// tdd control related
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// tdd counter related
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reg [23:0] tdd_counter = 24'h0;
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reg [ 5:0] tdd_burst_counter = 6'h0;
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reg tdd_cstate = OFF;
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reg tdd_cstate_next = OFF;
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reg counter_at_tdd_vco_rx_on_1 = 1'b0;
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reg counter_at_tdd_vco_rx_off_1 = 1'b0;
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reg counter_at_tdd_vco_tx_on_1 = 1'b0;
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reg counter_at_tdd_vco_tx_off_1 = 1'b0;
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reg counter_at_tdd_rx_on_1 = 1'b0;
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reg counter_at_tdd_rx_off_1 = 1'b0;
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reg counter_at_tdd_rx_dp_on_1 = 1'b0;
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reg counter_at_tdd_rx_dp_off_1 = 1'b0;
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reg counter_at_tdd_tx_on_1 = 1'b0;
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reg counter_at_tdd_tx_off_1 = 1'b0;
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reg counter_at_tdd_tx_dp_on_1 = 1'b0;
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reg counter_at_tdd_tx_dp_off_1 = 1'b0;
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reg counter_at_tdd_vco_rx_on_2 = 1'b0;
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reg counter_at_tdd_vco_rx_off_2 = 1'b0;
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reg counter_at_tdd_vco_tx_on_2 = 1'b0;
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reg counter_at_tdd_vco_tx_off_2 = 1'b0;
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reg counter_at_tdd_rx_on_2 = 1'b0;
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reg counter_at_tdd_rx_off_2 = 1'b0;
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reg counter_at_tdd_rx_dp_on_2 = 1'b0;
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reg counter_at_tdd_rx_dp_off_2 = 1'b0;
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reg counter_at_tdd_tx_on_2 = 1'b0;
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reg counter_at_tdd_tx_off_2 = 1'b0;
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reg counter_at_tdd_tx_dp_on_2 = 1'b0;
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reg counter_at_tdd_tx_dp_off_2 = 1'b0;
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reg tdd_last_burst = 1'b0;
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reg tdd_sync_d1 = 1'b0;
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reg tdd_sync_d2 = 1'b0;
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reg tdd_sync_d3 = 1'b0;
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reg tdd_endof_frame = 1'b0;
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// internal signals
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wire [23:0] tdd_vco_rx_on_1_s;
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wire [23:0] tdd_vco_rx_off_1_s;
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wire [23:0] tdd_vco_tx_on_1_s;
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wire [23:0] tdd_vco_tx_off_1_s;
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wire [23:0] tdd_rx_on_1_s;
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wire [23:0] tdd_rx_off_1_s;
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wire [23:0] tdd_tx_on_1_s;
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wire [23:0] tdd_tx_off_1_s;
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wire [23:0] tdd_tx_dp_on_1_s;
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wire [23:0] tdd_tx_dp_off_1_s;
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wire [23:0] tdd_vco_rx_on_2_s;
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wire [23:0] tdd_vco_rx_off_2_s;
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wire [23:0] tdd_vco_tx_on_2_s;
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wire [23:0] tdd_vco_tx_off_2_s;
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wire [23:0] tdd_rx_on_2_s;
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wire [23:0] tdd_rx_off_2_s;
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wire [23:0] tdd_tx_on_2_s;
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wire [23:0] tdd_tx_off_2_s;
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wire [23:0] tdd_tx_dp_on_2_s;
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wire [23:0] tdd_tx_dp_off_2_s;
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wire tdd_endof_burst;
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wire tdd_txrx_only_en_s;
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assign tdd_counter_status = tdd_counter;
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// synchronization of tdd_sync
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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tdd_sync_d1 <= 1'b0;
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tdd_sync_d2 <= 1'b0;
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tdd_sync_d3 <= 1'b0;
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end else begin
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tdd_sync_d1 <= tdd_sync;
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tdd_sync_d2 <= tdd_sync_d1;
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tdd_sync_d3 <= tdd_sync_d2;
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end
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end
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// ***************************************************************************
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// tdd counter (state machine)
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// ***************************************************************************
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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tdd_cstate <= OFF;
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end else begin
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tdd_cstate <= tdd_cstate_next;
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end
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end
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always @* begin
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tdd_cstate_next <= tdd_cstate;
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case (tdd_cstate)
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ON : begin
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if ((tdd_enable == 1'b0) || (tdd_endof_burst == 1'b1)) begin
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tdd_cstate_next <= OFF;
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end
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end
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OFF : begin
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if(tdd_enable == 1'b1) begin
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tdd_cstate_next <= ((~tdd_sync_d3 & tdd_sync_d2) == 1'b1) ? ON : OFF;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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if (tdd_counter == (tdd_frame_length - 1'b1)) begin
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tdd_endof_frame <= 1'b1;
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end else begin
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tdd_endof_frame <= 1'b0;
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end
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end
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assign tdd_endof_burst = ((tdd_last_burst == 1'b1) && (tdd_endof_frame == 1'b1)) ? 1'b1 : 1'b0;
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// tdd free running counter
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always @(posedge clk) begin
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if (rst == 1'b1) begin
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tdd_counter <= tdd_counter_init;
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end else begin
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if (tdd_cstate == ON) begin
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if ((~tdd_sync_d3 & tdd_sync_d2) == 1'b1) begin
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tdd_counter <= 24'b0;
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end else begin
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tdd_counter <= (tdd_endof_frame == 1'b1) ? 24'b0 : tdd_counter + 1'b1;
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end
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end else begin
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tdd_counter <= tdd_counter_init;
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end
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end
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end
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// tdd burst counter
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always @(posedge clk) begin
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if (tdd_cstate == OFF) begin
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tdd_burst_counter <= tdd_burst_count;
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end else if ((tdd_burst_counter != 0) && (tdd_endof_frame == 1'b1)) begin
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tdd_burst_counter <= tdd_burst_counter - 1'b1;
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end
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end
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always @(posedge clk) begin
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tdd_last_burst <= (tdd_burst_counter == 6'b1) ? 1'b1 : 1'b0;
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end
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// ***************************************************************************
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// generate control signals
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// ***************************************************************************
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// start/stop rx vco
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_vco_rx_on_1 <= 1'b0;
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end else if(tdd_counter == tdd_vco_rx_on_1_s) begin
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counter_at_tdd_vco_rx_on_1 <= 1'b1;
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end else begin
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counter_at_tdd_vco_rx_on_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_vco_rx_on_2 <= 1'b0;
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end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_on_2_s)) begin
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counter_at_tdd_vco_rx_on_2 <= 1'b1;
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end else begin
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counter_at_tdd_vco_rx_on_2 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_vco_rx_off_1 <= 1'b0;
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end else if(tdd_counter == tdd_vco_rx_off_1_s) begin
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counter_at_tdd_vco_rx_off_1 <= 1'b1;
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end else begin
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counter_at_tdd_vco_rx_off_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_vco_rx_off_2 <= 1'b0;
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end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_off_2_s)) begin
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counter_at_tdd_vco_rx_off_2 <= 1'b1;
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end else begin
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counter_at_tdd_vco_rx_off_2 <= 1'b0;
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end
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end
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// start/stop tx vco
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_vco_tx_on_1 <= 1'b0;
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end else if(tdd_counter == tdd_vco_tx_on_1_s) begin
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counter_at_tdd_vco_tx_on_1 <= 1'b1;
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end else begin
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counter_at_tdd_vco_tx_on_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_vco_tx_on_2 <= 1'b0;
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end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_on_2_s)) begin
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counter_at_tdd_vco_tx_on_2 <= 1'b1;
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end else begin
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counter_at_tdd_vco_tx_on_2 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_vco_tx_off_1 <= 1'b0;
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end else if(tdd_counter == tdd_vco_tx_off_1_s) begin
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counter_at_tdd_vco_tx_off_1 <= 1'b1;
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end else begin
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counter_at_tdd_vco_tx_off_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_vco_tx_off_2 <= 1'b0;
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end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_off_2_s)) begin
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counter_at_tdd_vco_tx_off_2 <= 1'b1;
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end else begin
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counter_at_tdd_vco_tx_off_2 <= 1'b0;
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end
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end
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// start/stop rx rf path
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_rx_on_1 <= 1'b0;
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end else if(tdd_counter == tdd_rx_on_1_s) begin
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counter_at_tdd_rx_on_1 <= 1'b1;
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end else begin
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counter_at_tdd_rx_on_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_rx_on_2 <= 1'b0;
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end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_on_2_s)) begin
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counter_at_tdd_rx_on_2 <= 1'b1;
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end else begin
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counter_at_tdd_rx_on_2 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_rx_off_1 <= 1'b0;
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end else if(tdd_counter == tdd_rx_off_1_s) begin
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counter_at_tdd_rx_off_1 <= 1'b1;
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end else begin
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counter_at_tdd_rx_off_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_rx_off_2 <= 1'b0;
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end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_off_2_s)) begin
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counter_at_tdd_rx_off_2 <= 1'b1;
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end else begin
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counter_at_tdd_rx_off_2 <= 1'b0;
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end
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end
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// start/stop tx rf path
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_tx_on_1 <= 1'b0;
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end else if(tdd_counter == tdd_tx_on_1_s) begin
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counter_at_tdd_tx_on_1 <= 1'b1;
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end else begin
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counter_at_tdd_tx_on_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_tx_on_2 <= 1'b0;
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end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_on_2_s)) begin
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counter_at_tdd_tx_on_2 <= 1'b1;
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end else begin
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counter_at_tdd_tx_on_2 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_tx_off_1 <= 1'b0;
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end else if(tdd_counter == tdd_tx_off_1_s) begin
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counter_at_tdd_tx_off_1 <= 1'b1;
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end else begin
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counter_at_tdd_tx_off_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_tx_off_2 <= 1'b0;
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end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_off_2_s)) begin
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counter_at_tdd_tx_off_2 <= 1'b1;
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end else begin
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counter_at_tdd_tx_off_2 <= 1'b0;
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end
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end
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// start/stop tx data path
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_tx_dp_on_1 <= 1'b0;
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end else if(tdd_counter == tdd_tx_dp_on_1_s) begin
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counter_at_tdd_tx_dp_on_1 <= 1'b1;
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end else begin
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counter_at_tdd_tx_dp_on_1 <= 1'b0;
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end
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end
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always @(posedge clk) begin
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if(rst == 1'b1) begin
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counter_at_tdd_tx_dp_on_2 <= 1'b0;
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end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_on_2_s)) begin
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counter_at_tdd_tx_dp_on_2 <= 1'b1;
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end else begin
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counter_at_tdd_tx_dp_on_2 <= 1'b0;
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end
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end
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always @(posedge clk) begin
|
|
if(rst == 1'b1) begin
|
|
counter_at_tdd_tx_dp_off_1 <= 1'b0;
|
|
end else if(tdd_counter == tdd_tx_dp_off_1_s) begin
|
|
counter_at_tdd_tx_dp_off_1 <= 1'b1;
|
|
end else begin
|
|
counter_at_tdd_tx_dp_off_1 <= 1'b0;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if(rst == 1'b1) begin
|
|
counter_at_tdd_tx_dp_off_2 <= 1'b0;
|
|
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_off_2_s)) begin
|
|
counter_at_tdd_tx_dp_off_2 <= 1'b1;
|
|
end else begin
|
|
counter_at_tdd_tx_dp_off_2 <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// start/stop rx data path
|
|
always @(posedge clk) begin
|
|
if(rst == 1'b1) begin
|
|
counter_at_tdd_rx_dp_on_1 <= 1'b0;
|
|
end else if(tdd_counter == tdd_rx_dp_on_1) begin
|
|
counter_at_tdd_rx_dp_on_1 <= 1'b1;
|
|
end else begin
|
|
counter_at_tdd_rx_dp_on_1 <= 1'b0;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if(rst == 1'b1) begin
|
|
counter_at_tdd_rx_dp_on_2 <= 1'b0;
|
|
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_dp_on_2)) begin
|
|
counter_at_tdd_rx_dp_on_2 <= 1'b1;
|
|
end else begin
|
|
counter_at_tdd_rx_dp_on_2 <= 1'b0;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if(rst == 1'b1) begin
|
|
counter_at_tdd_rx_dp_off_1 <= 1'b0;
|
|
end else if(tdd_counter == tdd_rx_dp_off_1) begin
|
|
counter_at_tdd_rx_dp_off_1 <= 1'b1;
|
|
end else begin
|
|
counter_at_tdd_rx_dp_off_1 <= 1'b0;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if(rst == 1'b1) begin
|
|
counter_at_tdd_rx_dp_off_2 <= 1'b0;
|
|
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_dp_off_2)) begin
|
|
counter_at_tdd_rx_dp_off_2 <= 1'b1;
|
|
end else begin
|
|
counter_at_tdd_rx_dp_off_2 <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// control-path delay compensation
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_vco_rx_on_1_comp (
|
|
.clk(clk),
|
|
.A(tdd_vco_rx_on_1),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_vco_rx_on_1_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_vco_rx_off_1_comp (
|
|
.clk(clk),
|
|
.A(tdd_vco_rx_off_1),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_vco_rx_off_1_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_vco_tx_on_1_comp (
|
|
.clk(clk),
|
|
.A(tdd_vco_tx_on_1),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_vco_tx_on_1_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_vco_tx_off_1_comp (
|
|
.clk(clk),
|
|
.A(tdd_vco_tx_off_1),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_vco_tx_off_1_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_rx_on_1_comp (
|
|
.clk(clk),
|
|
.A(tdd_rx_on_1),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_rx_on_1_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_rx_off_1_comp (
|
|
.clk(clk),
|
|
.A(tdd_rx_off_1),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_rx_off_1_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_tx_on_1_comp (
|
|
.clk(clk),
|
|
.A(tdd_tx_on_1),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_tx_on_1_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_tx_off_1_comp (
|
|
.clk(clk),
|
|
.A(tdd_tx_off_1),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_tx_off_1_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_vco_rx_on_2_comp (
|
|
.clk(clk),
|
|
.A(tdd_vco_rx_on_2),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_vco_rx_on_2_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_vco_rx_off_2_comp (
|
|
.clk(clk),
|
|
.A(tdd_vco_rx_off_2),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_vco_rx_off_2_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_vco_tx_on_2_comp (
|
|
.clk(clk),
|
|
.A(tdd_vco_tx_on_2),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_vco_tx_on_2_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_vco_tx_off_2_comp (
|
|
.clk(clk),
|
|
.A(tdd_vco_tx_off_2),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_vco_tx_off_2_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_rx_on_2_comp (
|
|
.clk(clk),
|
|
.A(tdd_rx_on_2),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_rx_on_2_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_rx_off_2_comp (
|
|
.clk(clk),
|
|
.A(tdd_rx_off_2),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_rx_off_2_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_tx_on_2_comp (
|
|
.clk(clk),
|
|
.A(tdd_tx_on_2),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_tx_on_2_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(CONTROL_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_tx_off_2_comp (
|
|
.clk(clk),
|
|
.A(tdd_tx_off_2),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_tx_off_2_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
// internal data-path delay compensation
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(TX_DATA_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_tx_dp_on_1_comp (
|
|
.clk(clk),
|
|
.A(tdd_tx_dp_on_1),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_tx_dp_on_1_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(TX_DATA_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_tx_dp_on_2_comp (
|
|
.clk(clk),
|
|
.A(tdd_tx_dp_on_2),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_tx_dp_on_2_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(TX_DATA_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_tx_dp_off_1_comp (
|
|
.clk(clk),
|
|
.A(tdd_tx_dp_off_1),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_tx_dp_off_1_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
ad_addsub #(
|
|
.A_DATA_WIDTH(24),
|
|
.B_DATA_VALUE(TX_DATA_PATH_DELAY),
|
|
.ADD_OR_SUB_N(0)
|
|
) i_tx_dp_off_2_comp (
|
|
.clk(clk),
|
|
.A(tdd_tx_dp_off_2),
|
|
.Amax(tdd_frame_length),
|
|
.out(tdd_tx_dp_off_2_s),
|
|
.CE(1'b1)
|
|
);
|
|
|
|
// output logic
|
|
|
|
assign tdd_txrx_only_en_s = tdd_tx_only ^ tdd_rx_only;
|
|
|
|
always @(posedge clk) begin
|
|
if(rst == 1'b1) begin
|
|
tdd_rx_vco_en <= 1'b0;
|
|
end else if((tdd_cstate == OFF) || (counter_at_tdd_vco_rx_off_1 == 1'b1) || (counter_at_tdd_vco_rx_off_2 == 1'b1)) begin
|
|
tdd_rx_vco_en <= 1'b0;
|
|
end else if((tdd_cstate == ON) && ((counter_at_tdd_vco_rx_on_1 == 1'b1) || (counter_at_tdd_vco_rx_on_2 == 1'b1))) begin
|
|
tdd_rx_vco_en <= 1'b1;
|
|
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
|
|
tdd_rx_vco_en <= tdd_rx_only;
|
|
end else begin
|
|
tdd_rx_vco_en <= tdd_rx_vco_en;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if(rst == 1'b1) begin
|
|
tdd_tx_vco_en <= 1'b0;
|
|
end else if((tdd_cstate == OFF) || (counter_at_tdd_vco_tx_off_1 == 1'b1) || (counter_at_tdd_vco_tx_off_2 == 1'b1)) begin
|
|
tdd_tx_vco_en <= 1'b0;
|
|
end else if((tdd_cstate == ON) && ((counter_at_tdd_vco_tx_on_1 == 1'b1) || (counter_at_tdd_vco_tx_on_2 == 1'b1))) begin
|
|
tdd_tx_vco_en <= 1'b1;
|
|
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
|
|
tdd_tx_vco_en <= tdd_tx_only;
|
|
end else begin
|
|
tdd_tx_vco_en <= tdd_tx_vco_en;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if(rst == 1'b1) begin
|
|
tdd_rx_rf_en <= 1'b0;
|
|
end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin
|
|
tdd_rx_rf_en <= 1'b0;
|
|
end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin
|
|
tdd_rx_rf_en <= 1'b1;
|
|
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
|
|
tdd_rx_rf_en <= tdd_rx_only;
|
|
end else begin
|
|
tdd_rx_rf_en <= tdd_rx_rf_en;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if(rst == 1'b1) begin
|
|
tdd_tx_rf_en <= 1'b0;
|
|
end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin
|
|
tdd_tx_rf_en <= 1'b0;
|
|
end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin
|
|
tdd_tx_rf_en <= 1'b1;
|
|
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
|
|
tdd_tx_rf_en <= tdd_tx_only;
|
|
end else begin
|
|
tdd_tx_rf_en <= tdd_tx_rf_en;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if(rst == 1'b1) begin
|
|
tdd_tx_dp_en <= 1'b0;
|
|
end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin
|
|
tdd_tx_dp_en <= 1'b0;
|
|
end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin
|
|
tdd_tx_dp_en <= 1'b1;
|
|
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
|
|
tdd_tx_dp_en <= tdd_tx_only;
|
|
end else begin
|
|
tdd_tx_dp_en <= tdd_tx_dp_en;
|
|
end
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
if(rst == 1'b1) begin
|
|
tdd_rx_dp_en <= 1'b0;
|
|
end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_dp_off_1 == 1'b1) || (counter_at_tdd_rx_dp_off_2 == 1'b1)) begin
|
|
tdd_rx_dp_en <= 1'b0;
|
|
end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_dp_on_1 == 1'b1) || (counter_at_tdd_rx_dp_on_2 == 1'b1))) begin
|
|
tdd_rx_dp_en <= 1'b1;
|
|
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
|
|
tdd_rx_dp_en <= tdd_rx_only;
|
|
end else begin
|
|
tdd_rx_dp_en <= tdd_rx_dp_en;
|
|
end
|
|
end
|
|
|
|
endmodule
|
|
|