8f61e11a70
For reliable and correct operation it is vital that the FPGA is fully configured and up and running before the PCIe host de-asserts the reset. Add a small logic circuit that detects de-assertion of the reset signal that can be used to verify that the reset de-assertion was seen by the FPGA. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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ccbrk | ||
ccbrk_cmos | ||
ccfmc | ||
ccpci | ||
common | ||
Makefile |