pluto_hdl_adi/projects/pzsdr
Lars-Peter Clausen 8f61e11a70 pzsdr: ccpci: Add PCIe reset monitor
For reliable and correct operation it is vital that the FPGA is fully
configured and up and running before the PCIe host de-asserts the reset.

Add a small logic circuit that detects de-assertion of the reset signal
that can be used to verify that the reset de-assertion was seen by the
FPGA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2016-08-05 18:31:40 +02:00
..
ccbrk pzsdr: Remove LED and button signals from PCIe carrier 2016-08-05 18:31:40 +02:00
ccbrk_cmos pzsdr: Remove LED and button signals from PCIe carrier 2016-08-05 18:31:40 +02:00
ccfmc pzsdr: Remove LED and button signals from PCIe carrier 2016-08-05 18:31:40 +02:00
ccpci pzsdr: ccpci: Add PCIe reset monitor 2016-08-05 18:31:40 +02:00
common hdl-vivado-2016.2: Update fmcomms2 and pzsdr base design 2016-08-01 13:49:12 +03:00
Makefile make updates 2016-04-11 16:14:59 -04:00