Laszlo Nagy 64f6762a05 library:axi_adrv9001: Initial version ... ADRV9001 interfacing IP supports the following modes on Xilinx devices: A B C D E F G H CSSI__1-lane 1 32 80 80 2.5 SDR 8 CSSI__1-lane 1 32 160 80 5 DDR 4 CSSI__4-lane 4 8 80 80 10 SDR 2 CSSI__4-lane 4 8 160 80 20 DDR 1 LSSI__1-lane 1 32 983.04 491.52 30.72 DDR 4 LSSI__2-lane 2 16 983.04 491.52 61.44 DDR 2 Columns description: A - SSI Modes B - Data Lanes Per Channel C - Serialization factor Per data lane D - Max data lane rate(MHz) E - Max Clock rate (MHz) F - Max Sample Rate for I/Q (MHz) G - Data Type H - DDS Rate CSSI - CMOS Source Synchronous Interface LSSI - LVDS Source Synchronous Interface Intel devices supports only CSSI modes.		2020-08-24 17:49:12 +03:00
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adrv9001_rx.v	library:axi_adrv9001: Initial version	2020-08-24 17:49:12 +03:00
adrv9001_tx.v	library:axi_adrv9001: Initial version	2020-08-24 17:49:12 +03:00