215 lines
7.0 KiB
Verilog
215 lines
7.0 KiB
Verilog
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module prcfg_adc (
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clk,
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// control ports
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control,
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status,
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// FIFO interface
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src_adc_dwr,
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src_adc_dsync,
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src_adc_ddata,
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src_adc_dovf,
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dst_adc_dwr,
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dst_adc_dsync,
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dst_adc_ddata,
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dst_adc_dovf
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);
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parameter CHANNEL_ID = 0;
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parameter DATA_WIDTH = 32;
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parameter SYMBOL_WIDTH = 2;
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localparam RP_ID = 8'hA2;
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localparam SYMBOLE_CNTR_WIDTH = $clog2(DATA_WIDTH/SYMBOLE_WIDTH);
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localparam NROF_SYMBOLS = DATA_WIDTH/SYMBOL_WIDTH;
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input clk;
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input [31:0] control;
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output [31:0] status;
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input src_adc_dwr;
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input src_adc_dsync;
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input [(DATA_WIDTH-1):0] src_adc_ddata;
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output src_adc_dovf;
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output dst_adc_dwr;
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output dst_adc_dsync;
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output [(DATA_WIDTH-1):0] dst_adc_ddata;
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input dst_adc_dovf;
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reg src_adc_dovf = 'h0;
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reg dst_adc_dwr = 'h0;
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reg dst_adc_dsync = 'h0;
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reg [(DATA_WIDTH-1):0] dst_adc_ddata = 'h0;
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reg [(DATA_WIDTH-1):0] adc_ddata = 'h0;
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reg [ 7:0] adc_pn_data = 'hF1;
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reg [31:0] status = 'h0;
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reg [ 3:0] mode = 'h0;
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reg [ 3:0] channel_sel = 'h0;
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reg [(SYMBOL_WIDTH-1):0] adc_data_buf[(NROF_SYMBOLS-1):0];
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reg [(SYMBOL_CNTR_WIDTH-1):0] symbole_counter = 'h0;
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reg [2:0] sample_counter = 'd0;
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wire adc_dvalid;
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wire dma_dvalid;
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wire [(SYMBOL_WIDTH-1):0] adc_ddata_s;
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wire adc_pn_err_s;
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wire adc_pn_oos_s;
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wire demod_en;
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// prbs function
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function [ 7:0] pn;
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input [ 7:0] din;
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reg [ 7:0] dout;
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begin
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dout[7] = din[6];
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dout[6] = din[5];
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dout[5] = din[4];
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dout[4] = din[3];
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dout[3] = din[2];
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dout[2] = din[1];
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dout[1] = din[7] ^ din[4];
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dout[0] = din[6] ^ din[3];
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pn = dout;
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end
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endfunction
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// update control and status registers
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always @(posedge clk) begin
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channel_sel <= control[ 3:0];
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mode <= control[ 7:4];
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end
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assign adc_dvalid = src_adc_dwr & src_adc_dsync;
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// data concatanation (MSB first)
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always @(posedge clk) begin
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if(adc_dvalid == 1'b1) begin
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adc_data_buf[(NROF_SYMBOLS - symbole_counter - 1)] <= adc_ddata_s;
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end
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end
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genvar i;
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generate
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for (i=0; i < NROF_SYMBOLS; i = i + 1) begin: SYMBOL_WRAPPER
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always @(posedge clk) begin
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if((adc_dvalid == 1'b1) &&
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(& symbole_counter == 1'b1) &&
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(sample_counter == 'b1) &&
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(mode != 0)) begin
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adc_ddata[((i+1)*SYMBOL_WIDTH)-1:(i*SYMBOL_WIDTH)] <= adc_data_buf[i];
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end
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end
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end
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endgenerate
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ad_pnmon #(
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.DATA_WIDTH(8)
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) i_pn_mon (
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.adc_clk(clk),
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.adc_valid_in(adc_dvalid),
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.adc_data_in({adc_pn_data[7:2], adc_ddata_s}),
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.adc_data_pn(adc_pn_data),
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.adc_pn_oos(adc_pn_oos_s),
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.adc_pn_err(adc_pn_err_s));
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// prbs generation
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always @(posedge clk) begin
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if(adc_dvalid == 1'b1) begin
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adc_pn_data <= pn(adc_pn_data);
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end
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end
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always @(posedge clk) begin
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if(adc_dvalid == 1'b1) begin
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if(demod_en == 1'b1) begin
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symbole_counter <= symbole_counter + 1;
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end
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sample_counter <= sample_counter + 1;
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end
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end
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assign demod_en = (sample_counter == 7) ? 1'b1 : 1'b0;
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// qpsk demodulator
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qpsk_demod i_qpsk_demod1 (
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.clk(clk),
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.data_qpsk_i(src_adc_ddata[15: 0]),
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.data_qpsk_q(src_adc_ddata[31:16]),
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.data_valid(adc_dvalid),
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.data_output(adc_ddata_s)
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);
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// output logic for data ans status
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always @(posedge clk) begin
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src_adc_dovf <= dst_adc_dovf;
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dst_adc_dsync <= src_adc_dsync;
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if(mode == 0) begin
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dst_adc_dwr <= src_adc_dwr;
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dst_adc_ddata <= src_adc_ddata;
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end else begin
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dst_adc_ddata <= adc_ddata;
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dst_adc_dwr <= (& symbole_counter) & (& sample_counter);
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end
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if((mode == 3'd2) && (channel_sel == CHANNEL_ID)) begin
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status <= {22'h0, adc_pn_err_s, adc_pn_oos_s, RP_ID};
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end else begin
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status <= {24'h0, RP_ID};
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end
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end
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endmodule
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