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Istvan Csomortani 8ecdb4a4ca library/tdd_control: Add common registers to the register map and fix init value of a register 
+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
 		2015-10-16 11:57:54 +03:00
library library/tdd_control: Add common registers to the register map and fix init value of a register 2015-10-16 11:57:54 +03:00
projects pzsdr/all: Update Makefile 2015-10-16 11:57:51 +03:00
.gitattributes Add .gitattributes file 2015-06-26 11:07:10 +02:00
.gitignore ignore gui 2015-09-22 16:32:02 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update Vivado's version number 2015-09-29 15:11:10 +03:00

README.md

#HDL Reference Designs

Analog Devices HDL libraries and projects

###Tools version:

###Documentation and support

For first time users, it is highly recommended to go through our HDL user guide.

For support please visit our FPGA Reference Designs Support Community on EngineerZone.