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pluto_hdl_adi/library/altera/common
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AndreiGrozav 568f2e180f ad_mul.v: Add parameters for A and B input widths 
The out width will be A + B.
This change is backward compatible and it applies to both Altera and Xilinx.
 		2018-07-18 18:19:30 +03:00
..
alt_ifconv Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
alt_mem_asym Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
alt_mul Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
alt_serdes Move Altera IP core dependency tracking to library Makefiles 2018-04-11 15:09:54 +03:00
ad_dcfilter.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
ad_mul.v ad_mul.v: Add parameters for A and B input widths 2018-07-18 18:19:30 +03:00
up_clock_mon_constr.sdc up_clock_mon- name changes 2017-06-06 11:36:18 -04:00
up_rst_constr.sdc constraints: Split the regmap CDC constraint into separate file 2017-05-25 15:12:16 +03:00
up_xfer_cntrl_constr.sdc constraints: Split the regmap CDC constraint into separate file 2017-05-25 15:12:16 +03:00
up_xfer_status_constr.sdc constraints: Split the regmap CDC constraint into separate file 2017-05-25 15:12:16 +03:00