229 lines
7.8 KiB
Verilog
229 lines
7.8 KiB
Verilog
// -----------------------------------------------------------------------------
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//
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED
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// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY
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// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// -----------------------------------------------------------------------------
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// FILE NAME : delay_30_degrees.v
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// MODULE NAME : delay_30_degrees
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// AUTHOR : ACostina
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// AUTHOR'S EMAIL : adrian.costina@analog.com
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// -----------------------------------------------------------------------------
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// KEYWORDS : BEMF, Analog Devices, Motor Control
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// -----------------------------------------------------------------------------
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// PURPOSE : Module used for delaying the BEMF based position signal with 30
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// degrees.
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// -----------------------------------------------------------------------------
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// REUSE ISSUES
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// Reset Strategy :
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// Clock Domains :
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// Critical Timing :
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// Test Features :
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// Asynchronous I/F :
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// Instantiations :
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// Synthesizable (y/n) :
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// Target Device :
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// Other :
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// -----------------------------------------------------------------------------
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`timescale 1ns / 1ps
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module delay_30_degrees
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//----------- Paramters Declarations -------------------------------------------
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//----------- Ports Declarations -----------------------------------------------
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(
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input clk_i,
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input rst_i,
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input [31:0] offset_i, // offset register
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input [2:0] position_i, // input position
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output reg [2:0] position_o // delayed with 30 degrees position
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);
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//------------------------------------------------------------------------------
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//----------- Local Parameters -------------------------------------------------
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//------------------------------------------------------------------------------
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localparam MAX_SPEED_COUNT = 32'h1000000;
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//State machine
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localparam RESET = 6'b000001;
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localparam INIT = 6'b000010;
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localparam CHANGE_POSITION = 6'b000100;
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localparam DELAY_30_DEGREES = 6'b001000;
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localparam APPLY_CHANGE = 6'b010000;
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localparam IDLE = 6'b100000;
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg [5:0] state; // current state
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reg [5:0] next_state; // next state
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reg [2:0] position_old; // saves the latest position
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reg [31:0] speed_count; // counts the current speed of rotation
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reg [31:0] speed_divider; // divides the speed of rotation by 2, correspoding to 30 degrees
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reg [31:0] delay_count; // Applied the delay to the input signal
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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// State transitions
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always @*
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begin
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next_state = state;
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case (state)
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RESET:
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begin
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next_state = INIT;
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end
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INIT:
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begin
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if (position_i != position_old)
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begin
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next_state = CHANGE_POSITION;
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end
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end
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CHANGE_POSITION:
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begin
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next_state = DELAY_30_DEGREES;
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end
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DELAY_30_DEGREES:
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begin
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if( delay_count > speed_divider)
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begin
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next_state = APPLY_CHANGE;
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end
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end
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APPLY_CHANGE:
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begin
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next_state = IDLE;
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end
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IDLE:
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begin
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if (position_i != position_old)
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begin
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next_state = CHANGE_POSITION;
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end
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end
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default:
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begin
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next_state = RESET;
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end
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endcase
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end
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always @(posedge clk_i)
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begin
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case(state)
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RESET:
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begin
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speed_count <= 0;
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speed_divider <= 0;
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position_o <= 3'b1;
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end
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INIT:
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begin
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if (speed_count < MAX_SPEED_COUNT)
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begin
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speed_count <= speed_count + 1;
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end
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end
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CHANGE_POSITION:
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begin
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speed_divider <= speed_count >> 1 ;
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speed_count <= 0;
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delay_count <= 0;
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end
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DELAY_30_DEGREES:
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begin
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if (speed_count < MAX_SPEED_COUNT)
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begin
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speed_count <= speed_count + 1;
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end
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delay_count <= delay_count + 1;
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end
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APPLY_CHANGE:
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begin
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if (position_i == 3'b101)
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begin
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position_o <= 100;
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end
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if (position_i == 3'b100)
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begin
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position_o <= 110;
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end
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if (position_i == 3'b110)
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begin
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position_o <= 010;
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end
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if (position_i == 3'b010)
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begin
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position_o <= 011;
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end
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if (position_i == 3'b011)
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begin
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position_o <= 001;
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end
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if (position_i == 3'b001)
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begin
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position_o <= 101;
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end
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position_old <= position_i;
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if (speed_count < MAX_SPEED_COUNT)
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begin
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speed_count <= speed_count + 1;
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end
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end
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IDLE:
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begin
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if (speed_count < MAX_SPEED_COUNT)
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begin
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speed_count <= speed_count + 1;
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end
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end
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endcase
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end
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always @ (posedge clk_i)
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begin
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if(rst_i == 1'b1)
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begin
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state <= RESET;
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end
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else
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begin
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state <= next_state;
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end
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end
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endmodule
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