pluto_hdl_adi/library/prcfg/qpsk/QPSK_Modulator_Baseband.v

66 lines
2.0 KiB
Verilog

// -------------------------------------------------------------
//
// File Name: hdlsrc\qpsk\QPSK_Modulator_Baseband.v
// Created: 2014-10-24 12:50:40
//
// Generated by MATLAB 8.3 and HDL Coder 3.4
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: QPSK_Modulator_Baseband
// Source Path: qpsk/Subsystem/QPSK Modulator Baseband
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module QPSK_Modulator_Baseband
(
in0,
out0_re,
out0_im
);
input [7:0] in0; // uint8
output signed [15:0] out0_re; // sfix16_En15
output signed [15:0] out0_im; // sfix16_En15
parameter signed [15:0] t1_re_0 = 23170; // sfix16
parameter signed [15:0] t1_re_1 = -23170; // sfix16
parameter signed [15:0] t1_re_2 = 23170; // sfix16
parameter signed [15:0] t1_re_3 = -23170; // sfix16
parameter signed [15:0] t1_im_0 = 23170; // sfix16
parameter signed [15:0] t1_im_1 = 23170; // sfix16
parameter signed [15:0] t1_im_2 = -23170; // sfix16
parameter signed [15:0] t1_im_3 = -23170; // sfix16
wire [1:0] constellationLUTaddress; // ufix2
wire signed [15:0] constellationLUT_t1_re [0:3]; // sfix16_En15 [4]
wire signed [15:0] constellationLUT_t1_im [0:3]; // sfix16_En15 [4]
assign constellationLUTaddress = in0[1:0];
assign constellationLUT_t1_re[0] = t1_re_0;
assign constellationLUT_t1_re[1] = t1_re_1;
assign constellationLUT_t1_re[2] = t1_re_2;
assign constellationLUT_t1_re[3] = t1_re_3;
assign constellationLUT_t1_im[0] = t1_im_0;
assign constellationLUT_t1_im[1] = t1_im_1;
assign constellationLUT_t1_im[2] = t1_im_2;
assign constellationLUT_t1_im[3] = t1_im_3;
assign out0_re = constellationLUT_t1_re[constellationLUTaddress];
assign out0_im = constellationLUT_t1_im[constellationLUTaddress];
endmodule // QPSK_Modulator_Baseband