267 lines
9.8 KiB
Verilog
267 lines
9.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_xcvr_rx_rst (
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// clock, reset and pll locked
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rx_clk,
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rx_rstn,
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rx_sw_rstn,
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rx_pll_locked,
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// xcvr status and reset
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rx_cal_busy,
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rx_cdr_locked,
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rx_analog_reset,
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rx_digital_reset,
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rx_ready,
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rx_rst_state);
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// parameters
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parameter NUM_OF_LANES = 4;
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parameter RX_CAL_DONE_COUNT_WIDTH = 8;
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parameter RX_CDR_LOCKED_COUNT_WIDTH = 8;
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parameter RX_ANALOG_RESET_COUNT_WIDTH = 5;
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parameter RX_DIGITAL_RESET_COUNT_WIDTH = 12;
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localparam RX_RESET_FSM_INIT = 4'h0;
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localparam RX_RESET_FSM_ARST0 = 4'h1;
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localparam RX_RESET_FSM_ARST1 = 4'h2;
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localparam RX_RESET_FSM_ARST2 = 4'h3;
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localparam RX_RESET_FSM_ARST3 = 4'h4;
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localparam RX_RESET_FSM_ARSTD = 4'h5;
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localparam RX_RESET_FSM_DRST0 = 4'h6;
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localparam RX_RESET_FSM_DRST1 = 4'h7;
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localparam RX_RESET_FSM_DRST2 = 4'h8;
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localparam RX_RESET_FSM_DRST3 = 4'h9;
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localparam RX_RESET_FSM_DRSTD = 4'ha;
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localparam RX_RESET_FSM_IDLE = 4'hb;
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// clock, reset and pll locked
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input rx_clk;
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input rx_rstn;
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input rx_sw_rstn;
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input rx_pll_locked;
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// xcvr status and reset
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input [NUM_OF_LANES-1:0] rx_cal_busy;
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input [NUM_OF_LANES-1:0] rx_cdr_locked;
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output [NUM_OF_LANES-1:0] rx_analog_reset;
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output [NUM_OF_LANES-1:0] rx_digital_reset;
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output rx_ready;
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output [ 3:0] rx_rst_state;
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// internal registers
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reg [ 2:0] rx_rst_req_m = 'd0;
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reg rx_rst_req = 'd0;
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reg [RX_CAL_DONE_COUNT_WIDTH:0] rx_cal_done_cnt = 'd0;
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reg [RX_CDR_LOCKED_COUNT_WIDTH:0] rx_cdr_locked_cnt = 'd0;
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reg [RX_ANALOG_RESET_COUNT_WIDTH:0] rx_analog_reset_cnt = 'd0;
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reg [RX_DIGITAL_RESET_COUNT_WIDTH:0] rx_digital_reset_cnt = 'd0;
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reg [ 3:0] rx_rst_state = 'd0;
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reg [NUM_OF_LANES-1:0] rx_analog_reset = 'd0;
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reg [NUM_OF_LANES-1:0] rx_digital_reset = 'd0;
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reg rx_ready = 'd0;
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// internal signals
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wire rx_rst_req_s;
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wire rx_cal_busy_s;
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wire rx_cal_done_s;
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wire rx_cal_done_valid_s;
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wire rx_cdr_locked_s;
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wire rx_cdr_locked_valid_s;
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wire rx_analog_reset_s;
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wire rx_analog_reset_valid_s;
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wire rx_digital_reset_s;
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wire rx_digital_reset_valid_s;
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// reset request
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assign rx_rst_req_s = ~(rx_rstn & rx_sw_rstn & rx_pll_locked);
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always @(posedge rx_clk) begin
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rx_rst_req_m <= {rx_rst_req_m[1:0], rx_rst_req_s};
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rx_rst_req <= rx_rst_req_m[2];
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end
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// cal busy check width
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assign rx_cal_busy_s = | rx_cal_busy;
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assign rx_cal_done_s = ~rx_cal_busy_s;
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assign rx_cal_done_valid_s = rx_cal_done_cnt[RX_CAL_DONE_COUNT_WIDTH];
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always @(posedge rx_clk) begin
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if (rx_cal_done_s == 1'd0) begin
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rx_cal_done_cnt <= 'd0;
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end else if (rx_cal_done_cnt[RX_CAL_DONE_COUNT_WIDTH] == 1'b0) begin
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rx_cal_done_cnt <= rx_cal_done_cnt + 1'b1;
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end
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end
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// cdr locked check width
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assign rx_cdr_locked_s = | rx_cdr_locked;
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assign rx_cdr_locked_valid_s = rx_cdr_locked_cnt[RX_CDR_LOCKED_COUNT_WIDTH];
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always @(posedge rx_clk) begin
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if (rx_cdr_locked_s == 1'd0) begin
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rx_cdr_locked_cnt <= 'd0;
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end else if (rx_cdr_locked_cnt[RX_CDR_LOCKED_COUNT_WIDTH] == 1'b0) begin
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rx_cdr_locked_cnt <= rx_cdr_locked_cnt + 1'b1;
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end
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end
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// analog reset width
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assign rx_analog_reset_s = | rx_analog_reset;
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assign rx_analog_reset_valid_s = rx_analog_reset_cnt[RX_ANALOG_RESET_COUNT_WIDTH];
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always @(posedge rx_clk) begin
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if (rx_analog_reset_s == 1'd0) begin
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rx_analog_reset_cnt <= 'd0;
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end else if (rx_analog_reset_cnt[RX_ANALOG_RESET_COUNT_WIDTH] == 1'b0) begin
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rx_analog_reset_cnt <= rx_analog_reset_cnt + 1'b1;
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end
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end
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// digital reset width
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assign rx_digital_reset_s = | rx_digital_reset;
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assign rx_digital_reset_valid_s = rx_digital_reset_cnt[RX_DIGITAL_RESET_COUNT_WIDTH];
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always @(posedge rx_clk) begin
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if (rx_digital_reset_s == 1'd0) begin
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rx_digital_reset_cnt <= 'd0;
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end else if (rx_digital_reset_cnt[RX_DIGITAL_RESET_COUNT_WIDTH] == 1'b0) begin
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rx_digital_reset_cnt <= rx_digital_reset_cnt + 1'b1;
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end
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end
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// state machine
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always @(posedge rx_clk) begin
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if (rx_rst_req == 1'b1) begin
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rx_rst_state <= RX_RESET_FSM_INIT;
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end else begin
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case (rx_rst_state)
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RX_RESET_FSM_INIT: begin
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rx_rst_state <= RX_RESET_FSM_ARST0;
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end
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RX_RESET_FSM_ARST0: begin
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if ((rx_cal_done_valid_s == 1'b1) && (rx_analog_reset_valid_s == 1'b1)) begin
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rx_rst_state <= RX_RESET_FSM_ARST1;
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end else begin
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rx_rst_state <= RX_RESET_FSM_ARST0;
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end
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end
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RX_RESET_FSM_ARST1: begin
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rx_rst_state <= RX_RESET_FSM_ARST2;
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end
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RX_RESET_FSM_ARST2: begin
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rx_rst_state <= RX_RESET_FSM_ARST3;
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end
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RX_RESET_FSM_ARST3: begin
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rx_rst_state <= RX_RESET_FSM_ARSTD;
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end
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RX_RESET_FSM_ARSTD: begin
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rx_rst_state <= RX_RESET_FSM_DRST0;
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end
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RX_RESET_FSM_DRST0: begin
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if ((rx_cdr_locked_valid_s == 1'b1) && (rx_digital_reset_valid_s == 1'b1)) begin
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rx_rst_state <= RX_RESET_FSM_DRST1;
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end else begin
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rx_rst_state <= RX_RESET_FSM_DRST0;
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end
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end
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RX_RESET_FSM_DRST1: begin
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rx_rst_state <= RX_RESET_FSM_DRST2;
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end
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RX_RESET_FSM_DRST2: begin
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rx_rst_state <= RX_RESET_FSM_DRST3;
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end
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RX_RESET_FSM_DRST3: begin
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rx_rst_state <= RX_RESET_FSM_DRSTD;
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end
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RX_RESET_FSM_DRSTD: begin
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rx_rst_state <= RX_RESET_FSM_IDLE;
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end
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RX_RESET_FSM_IDLE: begin
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rx_rst_state <= RX_RESET_FSM_IDLE;
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end
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default: begin
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rx_rst_state <= RX_RESET_FSM_INIT;
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end
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endcase
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end
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end
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// output signals
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always @(posedge rx_clk) begin
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if (rx_rst_state == RX_RESET_FSM_INIT) begin
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rx_analog_reset <= {{NUM_OF_LANES{1'b1}}};
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end else if (rx_rst_state == RX_RESET_FSM_ARSTD) begin
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rx_analog_reset <= {{NUM_OF_LANES{1'b0}}};
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end
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if (rx_rst_state == RX_RESET_FSM_INIT) begin
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rx_digital_reset <= {{NUM_OF_LANES{1'b1}}};
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end else if (rx_rst_state == RX_RESET_FSM_DRSTD) begin
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rx_digital_reset <= {{NUM_OF_LANES{1'b0}}};
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end
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if (rx_rst_state == RX_RESET_FSM_IDLE) begin
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rx_ready <= 1'b1;
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end else begin
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rx_ready <= 1'b0;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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