124 lines
4.0 KiB
Verilog
124 lines
4.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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// Constraints : CH_CNT must be power of 2
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// Build a large mux from smaller ones defined by the MUX_SZ parameter
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// Use EN_REG to add a register at the output of the small muxes to help
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// timing closure.
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module ad_mux #(
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parameter CH_W = 16, // Width of input channel
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parameter CH_CNT = 64, // Number of input channels
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parameter REQ_MUX_SZ = 8, // Size of mux which acts as a building block
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parameter EN_REG = 1, // Enable register at output of each mux
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parameter DW = CH_W*CH_CNT
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) (
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input clk,
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input [DW-1:0] data_in,
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input [$clog2(CH_CNT)-1:0] ch_sel,
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output [CH_W-1:0] data_out
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);
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`define MIN(A,B) (A<B?A:B)
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localparam MUX_SZ = CH_CNT < REQ_MUX_SZ ? CH_CNT : REQ_MUX_SZ;
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localparam CLOG2_CH_CNT = $clog2(CH_CNT);
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localparam CLOG2_MUX_SZ = $clog2(MUX_SZ);
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localparam NUM_STAGES = ($clog2(CH_CNT) / $clog2(MUX_SZ)) + // divide and round up
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|($clog2(CH_CNT) % $clog2(MUX_SZ));
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wire [NUM_STAGES*DW+CH_W-1:0] mux_in;
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wire [NUM_STAGES*CLOG2_CH_CNT-1:0] ch_sel_pln;
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assign mux_in[DW-1:0] = data_in;
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assign ch_sel_pln[CLOG2_CH_CNT-1:0] = ch_sel;
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genvar i;
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genvar j;
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generate
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for (i = 0; i < NUM_STAGES; i = i + 1) begin: g_stage
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wire [CLOG2_CH_CNT-1:0] ch_sel_cur;
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assign ch_sel_cur = ch_sel_pln[i*CLOG2_CH_CNT+:CLOG2_CH_CNT];
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wire [CLOG2_MUX_SZ-1:0] ch_sel_w;
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assign ch_sel_w = ch_sel_cur >> i*CLOG2_MUX_SZ;
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if (EN_REG) begin
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reg [CLOG2_CH_CNT-1:0] ch_sel_d;
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always @(posedge clk) begin
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ch_sel_d <= ch_sel_cur;
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end
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if (i<NUM_STAGES-1) begin
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assign ch_sel_pln[(i+1)*CLOG2_CH_CNT+:CLOG2_CH_CNT] = ch_sel_d;
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end
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end else begin
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if (i<NUM_STAGES-1) begin
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assign ch_sel_pln[(i+1)*CLOG2_CH_CNT+:CLOG2_CH_CNT] = ch_sel_cur;
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end
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end
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localparam MAX_RANGE_PER_STAGE=MUX_SZ**(NUM_STAGES-i);
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for (j = 0; j < `MIN(MAX_RANGE_PER_STAGE,CH_CNT); j = j + MUX_SZ) begin: g_mux
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ad_mux_core #(
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.CH_W (CH_W),
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.CH_CNT (MUX_SZ),
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.EN_REG (EN_REG)
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) i_mux (
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.clk (clk),
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.data_in (mux_in[i*DW+j*CH_W+:MUX_SZ*CH_W]),
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.ch_sel (ch_sel_w),
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.data_out (mux_in[(i+1)*DW+(j/MUX_SZ)*CH_W+:CH_W])
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);
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end
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end
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endgenerate
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assign data_out = mux_in[NUM_STAGES*DW+:CH_W];
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endmodule
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