Lars-Peter Clausen e644a99648 util_axis_fifo: Fix some data width mismatches ... Make sure that the right hand side expression of assignments is not wider than the target signal. This avoids warnings about implicit truncations. None of these changes affect the behaviour, just fixes some warnings about implicit signal truncation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-08-01 15:22:29 +02:00
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Makefile	Create CDC helper library	2017-05-23 11:16:07 +02:00
address_gray.v	util_axis_fifo: Switch to Verilog-2001 style parameter declaration	2017-08-01 15:22:29 +02:00
address_gray_pipelined.v	util_axis_fifo: Fix some data width mismatches	2017-08-01 15:22:29 +02:00
address_sync.v	util_axis_fifo: Fix some data width mismatches	2017-08-01 15:22:29 +02:00
util_axis_fifo.v	util_axis_fifo: Switch to Verilog-2001 style parameter declaration	2017-08-01 15:22:29 +02:00
util_axis_fifo_ip.tcl	Create CDC helper library	2017-05-23 11:16:07 +02:00