190 lines
5.9 KiB
Tcl
190 lines
5.9 KiB
Tcl
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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# RX parameters
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if ![info exists RX_NUM_OF_LANES] {
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set RX_NUM_OF_LANES 4 ; # L
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}
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if ![info exists RX_NUM_OF_CONVERTERS] {
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set RX_NUM_OF_CONVERTERS 16 ; # M
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}
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if ![info exists RX_SAMPLES_PER_FRAME] {
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set RX_SAMPLES_PER_FRAME 1 ; # S
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}
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if ![info exists RX_SAMPLE_WIDTH] {
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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}
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set RX_OCTETS_PER_FRAME [expr $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_FRAME * $RX_SAMPLE_WIDTH / (8*$RX_NUM_OF_LANES)] ; # F
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set DPW [expr max(4,$RX_OCTETS_PER_FRAME)] ;# max(4,F)
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set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8 * $DPW / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] ; # L * 8* DPW /
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set adc_dma_data_width [expr $RX_NUM_OF_LANES * 8 * $DPW]
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# adc peripherals
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# rx_out_clk = ref_clk
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# qpll0 selected
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ad_ip_instance axi_adxcvr axi_ad9083_rx_xcvr [list \
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NUM_OF_LANES $RX_NUM_OF_LANES \
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QPLL_ENABLE 1 \
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TX_OR_RX_N 0 \
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SYS_CLK_SEL 3 \
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OUT_CLK_SEL 4 \
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]
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adi_axi_jesd204_rx_create axi_ad9083_rx_jesd $RX_NUM_OF_LANES
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ad_ip_parameter axi_ad9083_rx_jesd/rx CONFIG.SYSREF_IOB false
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ad_ip_parameter axi_ad9083_rx_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH $DPW
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ad_ip_instance util_cpack2 util_ad9083_rx_cpack [list \
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NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_rx_create rx_ad9083_tpl_core $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_ad9083_rx_dma [list \
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DMA_TYPE_SRC 2 \
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DMA_TYPE_DEST 0 \
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CYCLIC 0 \
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SYNC_TRANSFER_START 0 \
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DMA_2D_TRANSFER 0 \
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MAX_BYTES_PER_BURST 4096 \
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AXI_SLICE_DEST 1 \
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AXI_SLICE_SRC 1 \
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FIFO_SIZE 32\
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DMA_LENGTH_WIDTH 31 \
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DMA_DATA_WIDTH_DEST 128 \
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DMA_DATA_WIDTH_SRC $adc_dma_data_width \
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]
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# common cores
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# fPLLClkin = 500 MHz => RX_CLK25_DIV = 20
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# fPLLClkout = 5000 MHz
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# VCO = 10000 MHz - qpll0
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ad_ip_instance util_adxcvr util_ad9083_xcvr [list \
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RX_NUM_OF_LANES $RX_NUM_OF_LANES \
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TX_NUM_OF_LANES 0 \
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QPLL_FBDIV 40 \
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QPLL_REFCLK_DIV 2 \
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RX_OUT_DIV 1 \
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RX_CLK25_DIV 20 \
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POR_CFG 0x0 \
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QPLL_CFG0 0x391c \
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QPLL_CFG1 0x0000 \
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QPLL_CFG1_G3 0x0020 \
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QPLL_CFG2 0x0f80 \
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QPLL_CFG2_G3 0x0f80 \
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QPLL_CFG3 0x0120 \
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QPLL_CFG4 0x0002 \
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QPLL_CP 0x1f \
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QPLL_CP_G3 0x1f \
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QPLL_LPF 0x2ff \
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CH_HSPMUX 0x2424 \
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PREIQ_FREQ_BST 0 \
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RXPI_CFG0 0x0102 \
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RXPI_CFG1 0x15 \
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RXCDR_CFG0 0x3 \
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RXCDR_CFG2_GEN2 0x265 \
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RXCDR_CFG2_GEN4 0x164 \
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RXCDR_CFG3 0x12 \
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RXCDR_CFG3_GEN2 0x12 \
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RXCDR_CFG3_GEN3 0x12 \
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RXCDR_CFG3_GEN4 0x12 \
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RX_WIDEMODE_CDR 0x0 \
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]
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# xcvr interfaces
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set rx_ref_clk rx_ref_clk_0
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create_bd_port -dir I $rx_ref_clk
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create_bd_port -dir I rx_core_clk_0
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ad_connect $sys_cpu_resetn util_ad9083_xcvr/up_rstn
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ad_connect $sys_cpu_clk util_ad9083_xcvr/up_clk
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# Rx
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ad_connect ad9083_rx_device_clk rx_core_clk_0
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ad_connect ad9083_rx_link_clk util_ad9083_xcvr/rx_out_clk_0
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ad_xcvrcon util_ad9083_xcvr axi_ad9083_rx_xcvr axi_ad9083_rx_jesd {} ad9083_rx_link_clk ad9083_rx_device_clk
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ad_xcvrpll $rx_ref_clk util_ad9083_xcvr/qpll_ref_clk_0
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for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
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set ch [expr $i]
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ad_xcvrpll $rx_ref_clk util_ad9083_xcvr/cpll_ref_clk_$ch
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ad_xcvrpll axi_ad9083_rx_xcvr/up_pll_rst util_ad9083_xcvr/up_cpll_rst_$ch
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}
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ad_xcvrpll axi_ad9083_rx_xcvr/up_pll_rst util_ad9083_xcvr/up_qpll_rst_*
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ad_ip_instance clk_wiz dma_clk_generator
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ad_ip_parameter dma_clk_generator CONFIG.PRIMITIVE MMCM
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ad_ip_parameter dma_clk_generator CONFIG.RESET_TYPE ACTIVE_LOW
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ad_ip_parameter dma_clk_generator CONFIG.USE_LOCKED false
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ad_ip_parameter dma_clk_generator CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 332.9
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ad_ip_parameter dma_clk_generator CONFIG.PRIM_SOURCE No_buffer
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ad_connect $sys_cpu_clk dma_clk_generator/clk_in1
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ad_connect $sys_cpu_resetn dma_clk_generator/resetn
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set sys_dma_clk_pin [get_bd_pins -filter {DIR == O} -of [get_bd_nets $sys_dma_clk]]
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ad_disconnect $sys_dma_clk $sys_dma_clk_pin
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ad_connect $sys_dma_clk [get_bd_pins dma_clk_generator/clk_out1]
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ad_connect axi_ad9083_rx_dma/fifo_wr util_ad9083_rx_cpack/packed_fifo_wr
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# connections (adc)
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ad_connect $sys_dma_resetn axi_ad9083_rx_dma/m_dest_axi_aresetn
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ad_connect ad9083_rx_device_clk axi_ad9083_rx_dma/fifo_wr_clk
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ad_connect ad9083_rx_device_clk rx_ad9083_tpl_core/link_clk
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ad_connect ad9083_rx_device_clk util_ad9083_rx_cpack/clk
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ad_connect rx_ad9083_tpl_core/adc_tpl_core/adc_rst util_ad9083_rx_cpack/reset
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ad_connect axi_ad9083_rx_jesd/rx_sof rx_ad9083_tpl_core/link_sof
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ad_connect axi_ad9083_rx_jesd/rx_data_tdata rx_ad9083_tpl_core/link_data
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ad_connect axi_ad9083_rx_jesd/rx_data_tvalid rx_ad9083_tpl_core/link_valid
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ad_connect rx_ad9083_tpl_core/adc_valid_0 util_ad9083_rx_cpack/fifo_wr_en
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ad_connect rx_ad9083_tpl_core/adc_dovf util_ad9083_rx_cpack/fifo_wr_overflow
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for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect rx_ad9083_tpl_core/adc_enable_$i util_ad9083_rx_cpack/enable_$i
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ad_connect rx_ad9083_tpl_core/adc_data_$i util_ad9083_rx_cpack/fifo_wr_data_$i
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}
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A00000 rx_ad9083_tpl_core
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ad_cpu_interconnect 0x44A60000 axi_ad9083_rx_xcvr
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ad_cpu_interconnect 0x44AA0000 axi_ad9083_rx_jesd
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ad_cpu_interconnect 0x7c400000 axi_ad9083_rx_dma
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ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1
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ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9083_rx_xcvr/m_axi
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# interconnect (mem/dac)
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ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_dma_clk axi_ad9083_rx_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-12 mb-13 axi_ad9083_rx_jesd/irq
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ad_cpu_interrupt ps-13 mb-12 axi_ad9083_rx_dma/irq
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# Create dummy outputs for unused Rx lanes
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for {set i $RX_NUM_OF_LANES} {$i < 4} {incr i} {
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create_bd_port -dir I rx_data_${i}_n
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create_bd_port -dir I rx_data_${i}_p
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}
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