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Istvan Csomortani 85ffc25ec5 ad_tdd_sync: Update the synchronization logic 
The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
 		2015-09-09 12:31:58 +03:00
library ad_tdd_sync: Update the synchronization logic 2015-09-09 12:31:58 +03:00
projects adv7511: KC705, updated design so that the axi_hdmi_dma core has memory connection datawidth of 512 2015-09-08 16:43:40 +03:00
.gitattributes Add .gitattributes file 2015-07-01 18:43:51 +02:00
.gitignore ignore *.hw 2015-08-25 14:24:21 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update to Quartus 15.0. Removed release candidate note 2015-08-13 11:55:23 +03:00

README.md

#HDL Reference Designs

Analog Devices HDL libraries and projects

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###Documentation and support

For first time users, it is highly recommended to go through our HDL user guide.

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