69a23ecde3
Currently the TX lane mapping is implemented by having to connect tx_phy_s_* to the tx_ip_s_* and the tx_phy_d_* to the tx_ip_d_* signals in the system qsys file in the desired order. Re-work things so that instead the lane mapping is provided through the TX_LANE_MAP parameter. The parameter specifies in which order logical lanes are mapped onto the physical lanes. The appropriate connections are than made inside the core according to this parameter rather than having to manually connect the signals externally. In order to generate a 1-to-1 mapping the TX_LANE_MAP parameter can be left empty. This change slightly reduces the boiler-plate code that is necessary to setup the transceiver. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| a10gx | ||
| a10soc | ||
| common | ||
| zc706 | ||
| Makefile | ||