pluto_hdl_adi/library/common/util_pulse_gen.v

88 lines
3.6 KiB
Verilog

// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
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// are permitted provided that the following conditions are met:
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// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module util_pulse_gen #(
parameter PULSE_WIDTH = 7,
parameter PULSE_PERIOD = 100000000) (
input clk,
input rstn,
output reg pulse);
// internal registers
reg [(PULSE_WIDTH-1):0] pulse_width_cnt = {PULSE_WIDTH{1'b1}};
reg [31:0] pulse_period_cnt = 32'h0;
wire end_of_period_s;
// a free running pulse generator
always @(posedge clk) begin
if (rstn == 1'b0) begin
pulse_period_cnt <= 32'h0;
end else begin
pulse_period_cnt <= (pulse_period_cnt < PULSE_PERIOD) ? (pulse_period_cnt + 1) : 32'b0;
end
end
assign end_of_period_s = (pulse_period_cnt == (PULSE_PERIOD - 1)) ? 1'b1 : 1'b0;
// generate pulse with a specified width
always @(posedge clk) begin
if (rstn == 1'b0) begin
pulse_width_cnt <= 0;
pulse <= 0;
end else begin
pulse_width_cnt <= (pulse == 1'b1) ? pulse_width_cnt + 1 : {PULSE_WIDTH{1'h0}};
if(end_of_period_s == 1'b1) begin
pulse <= 1'b1;
end else if(pulse_width_cnt == {PULSE_WIDTH{1'b1}}) begin
pulse <= 1'b0;
end
end
end
endmodule