190 lines
6.3 KiB
Verilog
190 lines
6.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// This is the LVDS/DDR interface
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`timescale 1ns/100ps
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module axi_ad9467_if #(
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parameter DEVICE_TYPE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group") (
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// adc interface (clk, data, over-range)
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input adc_clk_in_p,
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input adc_clk_in_n,
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input [ 7:0] adc_data_in_p,
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input [ 7:0] adc_data_in_n,
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input adc_or_in_p,
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input adc_or_in_n,
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// interface outputs
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output adc_clk,
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output reg [15:0] adc_data,
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output reg adc_or,
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// processor interface
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input adc_ddr_edgesel,
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// delay control signals
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input up_clk,
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input [ 8:0] up_dld,
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input [44:0] up_dwdata,
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output [44:0] up_drdata,
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input delay_clk,
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input delay_rst,
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output delay_locked);
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// internal registers
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reg [ 7:0] adc_data_p = 'd0;
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reg [ 7:0] adc_data_n = 'd0;
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reg [ 7:0] adc_data_p_d = 'd0;
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reg [ 7:0] adc_dmux_a = 'd0;
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reg [ 7:0] adc_dmux_b = 'd0;
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reg adc_or_p = 'd0;
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reg adc_or_n = 'd0;
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// internal signals
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wire [ 7:0] adc_data_p_s;
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wire [ 7:0] adc_data_n_s;
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wire adc_or_p_s;
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wire adc_or_n_s;
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genvar l_inst;
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// sample select (p/n) swap
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always @(posedge adc_clk) begin
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adc_data_p <= adc_data_p_s;
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adc_data_n <= adc_data_n_s;
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adc_data_p_d <= adc_data_p;
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adc_dmux_a <= (adc_ddr_edgesel == 1'b1) ? adc_data_n : adc_data_p;
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adc_dmux_b <= (adc_ddr_edgesel == 1'b1) ? adc_data_p_d : adc_data_n;
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adc_data[15] <= adc_dmux_b[7];
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adc_data[14] <= adc_dmux_a[7];
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adc_data[13] <= adc_dmux_b[6];
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adc_data[12] <= adc_dmux_a[6];
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adc_data[11] <= adc_dmux_b[5];
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adc_data[10] <= adc_dmux_a[5];
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adc_data[ 9] <= adc_dmux_b[4];
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adc_data[ 8] <= adc_dmux_a[4];
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adc_data[ 7] <= adc_dmux_b[3];
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adc_data[ 6] <= adc_dmux_a[3];
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adc_data[ 5] <= adc_dmux_b[2];
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adc_data[ 4] <= adc_dmux_a[2];
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adc_data[ 3] <= adc_dmux_b[1];
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adc_data[ 2] <= adc_dmux_a[1];
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adc_data[ 1] <= adc_dmux_b[0];
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adc_data[ 0] <= adc_dmux_a[0];
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adc_or_p <= adc_or_p_s;
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adc_or_n <= adc_or_n_s;
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if ((adc_or_p == 1'b1) || (adc_or_n == 1'b1)) begin
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adc_or <= 1'b1;
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end else begin
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adc_or <= 1'b0;
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end
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end
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// data interface
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generate
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for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
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ad_lvds_in #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.IODELAY_CTRL (0),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_adc_data (
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.rx_clk (adc_clk),
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.rx_data_in_p (adc_data_in_p[l_inst]),
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.rx_data_in_n (adc_data_in_n[l_inst]),
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.rx_data_p (adc_data_p_s[l_inst]),
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.rx_data_n (adc_data_n_s[l_inst]),
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.up_clk (up_clk),
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.up_dld (up_dld[l_inst]),
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.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
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.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked ());
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end
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endgenerate
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// over-range interface
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ad_lvds_in #(
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.DEVICE_TYPE (DEVICE_TYPE),
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.IODELAY_CTRL (1),
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.IODELAY_GROUP (IO_DELAY_GROUP))
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i_adc_or (
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.rx_clk (adc_clk),
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.rx_data_in_p (adc_or_in_p),
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.rx_data_in_n (adc_or_in_n),
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.rx_data_p (adc_or_p_s),
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.rx_data_n (adc_or_n_s),
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.up_clk (up_clk),
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.up_dld (up_dld[8]),
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.up_dwdata (up_dwdata[44:40]),
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.up_drdata (up_drdata[44:40]),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_locked (delay_locked));
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// clock
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ad_lvds_clk #(
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.DEVICE_TYPE (DEVICE_TYPE))
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i_adc_clk (
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.rst (1'b0),
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.locked (),
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.clk_in_p (adc_clk_in_p),
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.clk_in_n (adc_clk_in_n),
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.clk (adc_clk));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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