18 lines
450 B
Tcl
18 lines
450 B
Tcl
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source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
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# specify the spi reference clock frequency in MHz
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set spi_clk_ref_frequency 166
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# specify ADC resolution -- supported resolutions 16/18/20 bits
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set adc_resolution 20
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# specify ADC sampling rate in samples/seconds
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# NOTE: This rate can be set just in turbo mode -- if turbo mode is not used
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# the max rate should be 1.6 MSPS
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set adc_sampling_rate 1800000
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source ../common/ad40xx_bd.tcl
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