828 lines
71 KiB
Tcl
828 lines
71 KiB
Tcl
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# device settings
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set_global_assignment -name FAMILY "Arria V"
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set_global_assignment -name DEVICE 5AGTFD7K3F40I3
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# clocks and resets
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set_location_assignment PIN_C34 -to sys_clk
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set_location_assignment PIN_D34 -to "sys_clk(n)"
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set_instance_assignment -name IO_STANDARD LVDS -to sys_clk
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sys_clk -disable
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set_location_assignment PIN_L6 -to sys_resetn
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set_instance_assignment -name IO_STANDARD "2.5 V" -to sys_resetn
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# ddr3
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set_location_assignment PIN_B31 -to ddr3_a[0]
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set_location_assignment PIN_A30 -to ddr3_a[1]
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set_location_assignment PIN_A31 -to ddr3_a[2]
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set_location_assignment PIN_A32 -to ddr3_a[3]
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set_location_assignment PIN_A33 -to ddr3_a[4]
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set_location_assignment PIN_B33 -to ddr3_a[5]
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set_location_assignment PIN_H31 -to ddr3_a[6]
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set_location_assignment PIN_J31 -to ddr3_a[7]
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set_location_assignment PIN_C31 -to ddr3_a[8]
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set_location_assignment PIN_D31 -to ddr3_a[9]
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set_location_assignment PIN_C32 -to ddr3_a[10]
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set_location_assignment PIN_D32 -to ddr3_a[11]
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set_location_assignment PIN_N31 -to ddr3_a[12]
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set_location_assignment PIN_P31 -to ddr3_a[13]
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set_location_assignment PIN_M32 -to ddr3_ba[0]
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set_location_assignment PIN_N32 -to ddr3_ba[1]
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set_location_assignment PIN_J34 -to ddr3_ba[2]
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set_location_assignment PIN_B30 -to ddr3_clk_p
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set_location_assignment PIN_C30 -to ddr3_clk_n
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set_location_assignment PIN_E31 -to ddr3_cke
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set_location_assignment PIN_L34 -to ddr3_cs_n
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set_location_assignment PIN_K34 -to ddr3_ras_n
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set_location_assignment PIN_L33 -to ddr3_cas_n
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set_location_assignment PIN_M33 -to ddr3_we_n
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set_location_assignment PIN_G30 -to ddr3_reset_n
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set_location_assignment PIN_L31 -to ddr3_odt
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set_location_assignment PIN_F33 -to ddr3_rzq
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set_location_assignment PIN_N30 -to ddr3_dqs_p[0]
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set_location_assignment PIN_P30 -to ddr3_dqs_n[0]
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set_location_assignment PIN_R29 -to ddr3_dqs_p[1]
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set_location_assignment PIN_T29 -to ddr3_dqs_n[1]
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set_location_assignment PIN_J30 -to ddr3_dm[0]
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set_location_assignment PIN_J29 -to ddr3_dm[1]
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set_location_assignment PIN_B28 -to ddr3_dq[0]
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set_location_assignment PIN_C29 -to ddr3_dq[1]
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set_location_assignment PIN_R30 -to ddr3_dq[2]
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set_location_assignment PIN_A29 -to ddr3_dq[3]
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set_location_assignment PIN_A28 -to ddr3_dq[4]
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set_location_assignment PIN_L30 -to ddr3_dq[5]
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set_location_assignment PIN_D30 -to ddr3_dq[6]
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set_location_assignment PIN_D29 -to ddr3_dq[7]
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set_location_assignment PIN_L28 -to ddr3_dq[8]
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set_location_assignment PIN_M28 -to ddr3_dq[9]
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set_location_assignment PIN_H28 -to ddr3_dq[10]
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set_location_assignment PIN_C28 -to ddr3_dq[11]
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set_location_assignment PIN_D28 -to ddr3_dq[12]
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set_location_assignment PIN_F28 -to ddr3_dq[13]
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set_location_assignment PIN_M29 -to ddr3_dq[14]
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set_location_assignment PIN_N29 -to ddr3_dq[15]
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set_location_assignment PIN_R28 -to ddr3_dqs_p[2]
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set_location_assignment PIN_T28 -to ddr3_dqs_n[2]
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set_location_assignment PIN_M26 -to ddr3_dqs_p[3]
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set_location_assignment PIN_N26 -to ddr3_dqs_n[3]
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set_location_assignment PIN_K27 -to ddr3_dm[2]
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set_location_assignment PIN_J26 -to ddr3_dm[3]
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set_location_assignment PIN_P27 -to ddr3_dq[16]
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set_location_assignment PIN_R27 -to ddr3_dq[17]
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set_location_assignment PIN_H27 -to ddr3_dq[18]
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set_location_assignment PIN_B27 -to ddr3_dq[19]
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set_location_assignment PIN_C27 -to ddr3_dq[20]
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set_location_assignment PIN_E27 -to ddr3_dq[21]
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set_location_assignment PIN_M27 -to ddr3_dq[22]
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set_location_assignment PIN_N27 -to ddr3_dq[23]
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set_location_assignment PIN_C26 -to ddr3_dq[24]
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set_location_assignment PIN_D26 -to ddr3_dq[25]
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set_location_assignment PIN_K25 -to ddr3_dq[26]
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set_location_assignment PIN_R26 -to ddr3_dq[27]
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set_location_assignment PIN_T27 -to ddr3_dq[28]
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set_location_assignment PIN_A26 -to ddr3_dq[29]
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set_location_assignment PIN_F26 -to ddr3_dq[30]
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set_location_assignment PIN_G26 -to ddr3_dq[31]
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set_location_assignment PIN_A20 -to ddr3_dqs_p[4]
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set_location_assignment PIN_B21 -to ddr3_dqs_n[4]
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set_location_assignment PIN_C23 -to ddr3_dqs_p[5]
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set_location_assignment PIN_D23 -to ddr3_dqs_n[5]
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set_location_assignment PIN_M21 -to ddr3_dm[4]
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set_location_assignment PIN_B22 -to ddr3_dm[5]
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set_location_assignment PIN_D20 -to ddr3_dq[32]
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set_location_assignment PIN_H21 -to ddr3_dq[33]
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set_location_assignment PIN_D21 -to ddr3_dq[34]
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set_location_assignment PIN_J21 -to ddr3_dq[35]
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set_location_assignment PIN_A21 -to ddr3_dq[36]
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set_location_assignment PIN_G21 -to ddr3_dq[37]
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set_location_assignment PIN_A22 -to ddr3_dq[38]
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set_location_assignment PIN_C20 -to ddr3_dq[39]
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set_location_assignment PIN_A23 -to ddr3_dq[40]
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set_location_assignment PIN_E22 -to ddr3_dq[41]
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set_location_assignment PIN_L22 -to ddr3_dq[42]
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set_location_assignment PIN_C22 -to ddr3_dq[43]
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set_location_assignment PIN_N22 -to ddr3_dq[44]
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set_location_assignment PIN_F22 -to ddr3_dq[45]
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set_location_assignment PIN_P22 -to ddr3_dq[46]
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set_location_assignment PIN_J22 -to ddr3_dq[47]
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set_location_assignment PIN_D24 -to ddr3_dqs_p[6]
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set_location_assignment PIN_E24 -to ddr3_dqs_n[6]
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set_location_assignment PIN_A25 -to ddr3_dqs_p[7]
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set_location_assignment PIN_B25 -to ddr3_dqs_n[7]
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set_location_assignment PIN_J23 -to ddr3_dm[6]
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set_location_assignment PIN_D25 -to ddr3_dm[7]
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set_location_assignment PIN_C24 -to ddr3_dq[48]
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set_location_assignment PIN_M23 -to ddr3_dq[49]
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set_location_assignment PIN_B24 -to ddr3_dq[50]
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set_location_assignment PIN_R23 -to ddr3_dq[51]
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set_location_assignment PIN_G24 -to ddr3_dq[52]
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set_location_assignment PIN_G23 -to ddr3_dq[53]
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set_location_assignment PIN_F24 -to ddr3_dq[54]
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set_location_assignment PIN_F23 -to ddr3_dq[55]
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set_location_assignment PIN_R24 -to ddr3_dq[56]
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set_location_assignment PIN_G25 -to ddr3_dq[57]
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set_location_assignment PIN_T26 -to ddr3_dq[58]
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set_location_assignment PIN_E25 -to ddr3_dq[59]
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set_location_assignment PIN_N24 -to ddr3_dq[60]
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set_location_assignment PIN_K24 -to ddr3_dq[61]
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set_location_assignment PIN_T25 -to ddr3_dq[62]
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set_location_assignment PIN_P24 -to ddr3_dq[63]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[0]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[1]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[2]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[3]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[4]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[5]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[6]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[7]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[8]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[9]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[10]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[11]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[12]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_a[13]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[0]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[1]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ba[2]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_clk_p
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_clk_n
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cke
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cs_n
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_ras_n
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_cas_n
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_we_n
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_odt
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set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_reset_n
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set_instance_assignment -name IO_STANDARD "1.5 V" -to ddr3_rzq
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[0]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[0]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[1]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[1]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[0]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[1]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[0]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[1]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[2]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[3]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[4]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[5]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[6]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[7]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[8]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[9]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[10]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[11]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[12]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[13]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[14]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[15]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[2]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[2]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[3]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[3]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[2]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[3]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[16]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[17]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[18]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[19]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[20]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[21]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[22]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[23]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[24]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[25]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[26]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[27]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[28]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[29]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[30]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[31]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[4]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[4]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[5]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[5]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[4]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[5]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[32]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[33]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[34]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[35]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[36]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[37]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[38]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[39]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[40]
|
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[41]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[42]
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|
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[43]
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|
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[44]
|
|
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[45]
|
|
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[46]
|
|
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[47]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[6]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[6]
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set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_p[7]
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|
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_dqs_n[7]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[6]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dm[7]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[48]
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|
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[49]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[50]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[51]
|
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[52]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[53]
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|
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[54]
|
|
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[55]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[56]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[57]
|
|
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[58]
|
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[59]
|
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[60]
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set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[61]
|
|
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[62]
|
|
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[63]
|
|
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[0]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[1]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[2]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[3]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[4]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[5]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[6]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[7]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[8]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[9]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[10]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[11]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[12]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_a[13]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[0]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[1]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ba[2]
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cke
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cs_n
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_ras_n
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_cas_n
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_we_n
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_reset_n
|
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_odt
|
|
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dm[0]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dm[1]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[0]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[1]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[2]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[3]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[4]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[5]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[6]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[0] -to ddr3_dq[7]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[8]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[9]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[10]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[11]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[12]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[13]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[14]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[1] -to ddr3_dq[15]
|
|
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dm[2]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dm[3]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[16]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[17]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[18]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[19]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[20]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[21]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[22]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[2] -to ddr3_dq[23]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[24]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[25]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[26]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[27]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[28]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[29]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[30]
|
|
set_instance_assignment -name DQ_GROUP 9 -from ddr3_dqs_p[3] -to ddr3_dq[31]
|
|
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_clk_p
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_clk_n
|
|
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[0]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[0]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[1]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[1]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[0]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[1]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[0]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[1]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[2]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[3]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[4]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[5]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[6]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[7]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[8]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[9]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[10]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[11]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[12]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[13]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[14]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[15]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[0]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[1]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[2]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[3]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[4]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[5]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[6]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[7]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[8]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[9]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[10]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[11]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[12]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[13]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[14]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[15]
|
|
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[2]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[2]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[3]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[3]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[2]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[3]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[16]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[17]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[18]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[19]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[20]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[21]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[22]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[23]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[24]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[25]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[26]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[27]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[28]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[29]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[30]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[31]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[16]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[17]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[18]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[19]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[20]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[21]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[22]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[23]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[24]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[25]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[26]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[27]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[28]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[29]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[30]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[31]
|
|
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[5]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[5]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[4]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[4]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[5]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[5]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[4]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[5]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[32]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[33]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[34]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[35]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[36]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[37]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[38]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[39]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[40]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[41]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[42]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[43]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[44]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[45]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[46]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[47]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[32]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[33]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[34]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[35]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[36]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[37]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[38]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[39]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[40]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[41]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[42]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[43]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[44]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[45]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[46]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[47]
|
|
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[6]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[6]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[7]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[7]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[6]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[6]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_p[7]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dqs_n[7]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[6]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dm[7]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[48]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[49]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[50]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[51]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[52]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[53]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[54]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[55]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[56]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[57]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[58]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[59]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[60]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[61]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[62]
|
|
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[63]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[48]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[49]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[50]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[51]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[52]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[53]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[54]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[55]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[56]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[57]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[58]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[59]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[60]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[61]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[62]
|
|
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[63]
|
|
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[0]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[1]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[2]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[3]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[4]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[5]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[6]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[7]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[8]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[9]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[10]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[11]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[12]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_a[13]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[0]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[1]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ba[2]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_clk_p
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_clk_n
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cke
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cs_n
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_ras_n
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_cas_n
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_we_n
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_reset_n
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_odt
|
|
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[0]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[0]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[1]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[1]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[0]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[1]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[0]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[1]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[2]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[3]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[4]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[5]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[6]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[7]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[8]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[9]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[10]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[11]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[12]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[13]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[14]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[15]
|
|
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[2]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[2]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[3]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[3]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[2]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[3]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[16]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[17]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[18]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[19]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[20]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[21]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[22]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[23]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[24]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[25]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[26]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[27]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[28]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[29]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[30]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[31]
|
|
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[4]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[4]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[5]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[5]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[4]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[5]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[32]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[33]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[34]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[35]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[36]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[37]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[38]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[39]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[40]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[41]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[42]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[43]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[44]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[45]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[46]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[47]
|
|
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[6]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[6]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_p[7]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dqs_n[7]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[6]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dm[7]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[48]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[49]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[50]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[51]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[52]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[53]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[54]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[55]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[56]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[57]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[58]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[59]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[60]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[61]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[62]
|
|
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION ON -to ddr3_dq[63]
|
|
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[0]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[0]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[1]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[1]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[0]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[1]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[0]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[1]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[2]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[3]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[4]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[5]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[6]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[7]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[8]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[9]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[10]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[11]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[12]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[13]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[14]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[15]
|
|
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[2]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[2]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_p[3]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dqs_n[3]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[2]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dm[3]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[16]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[17]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[18]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[19]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[20]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[21]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[22]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[23]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[24]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[25]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[26]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[27]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[28]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[29]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[30]
|
|
set_instance_assignment -name MEM_INTERFACE_DELAY_CHAIN_CONFIG FLEXIBLE_TIMING -to ddr3_dq[31]
|
|
|
|
# ethernet interface
|
|
|
|
set_location_assignment PIN_A6 -to eth_rx_clk
|
|
set_location_assignment PIN_B6 -to "eth_rx_clk(n)"
|
|
set_location_assignment PIN_D13 -to eth_rx_cntrl
|
|
set_location_assignment PIN_E13 -to "eth_rx_cntrl(n)"
|
|
set_location_assignment PIN_A13 -to eth_rx_data[0]
|
|
set_location_assignment PIN_A12 -to "eth_rx_data[0](n)"
|
|
set_location_assignment PIN_D12 -to eth_rx_data[1]
|
|
set_location_assignment PIN_E12 -to "eth_rx_data[1](n)"
|
|
set_location_assignment PIN_P13 -to eth_rx_data[2]
|
|
set_location_assignment PIN_R13 -to "eth_rx_data[2](n)"
|
|
set_location_assignment PIN_B10 -to eth_rx_data[3]
|
|
set_location_assignment PIN_C10 -to "eth_rx_data[3](n)"
|
|
|
|
set_instance_assignment -name IO_STANDARD LVDS -to eth_rx_clk
|
|
set_instance_assignment -name IO_STANDARD LVDS -to eth_rx_cntrl
|
|
set_instance_assignment -name IO_STANDARD LVDS -to eth_rx_data
|
|
|
|
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_rx_clk
|
|
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_rx_cntrl
|
|
set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to eth_rx_data
|
|
|
|
set_location_assignment PIN_H18 -to eth_tx_clk_out
|
|
set_location_assignment PIN_J18 -to "eth_tx_clk_out(n)"
|
|
set_location_assignment PIN_J11 -to eth_tx_cntrl
|
|
set_location_assignment PIN_K11 -to "eth_tx_cntrl(n)"
|
|
set_location_assignment PIN_K12 -to eth_tx_data[0]
|
|
set_location_assignment PIN_L12 -to "eth_tx_data[0](n)"
|
|
set_location_assignment PIN_F12 -to eth_tx_data[1]
|
|
set_location_assignment PIN_G12 -to "eth_tx_data[1](n)"
|
|
set_location_assignment PIN_H10 -to eth_tx_data[2]
|
|
set_location_assignment PIN_J10 -to "eth_tx_data[2](n)"
|
|
set_location_assignment PIN_A14 -to eth_tx_data[3]
|
|
set_location_assignment PIN_B13 -to "eth_tx_data[3](n)"
|
|
|
|
set_instance_assignment -name IO_STANDARD LVDS -to eth_tx_clk_out
|
|
set_instance_assignment -name IO_STANDARD LVDS -to eth_tx_cntrl
|
|
set_instance_assignment -name IO_STANDARD LVDS -to eth_tx_data
|
|
|
|
set_location_assignment PIN_E15 -to eth_mdc
|
|
set_location_assignment PIN_F15 -to eth_mdio_i
|
|
set_location_assignment PIN_G16 -to eth_mdio_o
|
|
set_location_assignment PIN_H16 -to eth_mdio_t
|
|
set_location_assignment PIN_K18 -to eth_phy_resetn
|
|
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdc
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_i
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_o
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_t
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_phy_resetn
|
|
|
|
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to eth_rx_clk
|
|
|
|
# leds
|
|
|
|
set_location_assignment PIN_M19 -to gpio_bd_o[0] ; ## led_grn[0]
|
|
set_location_assignment PIN_L19 -to gpio_bd_o[1] ; ## led_grn[1]
|
|
set_location_assignment PIN_K19 -to gpio_bd_o[2] ; ## led_grn[2]
|
|
set_location_assignment PIN_J19 -to gpio_bd_o[3] ; ## led_grn[3]
|
|
set_location_assignment PIN_K20 -to gpio_bd_o[4] ; ## led_grn[4]
|
|
set_location_assignment PIN_J20 -to gpio_bd_o[5] ; ## led_grn[5]
|
|
set_location_assignment PIN_T20 -to gpio_bd_o[6] ; ## led_grn[6]
|
|
set_location_assignment PIN_R20 -to gpio_bd_o[7] ; ## led_grn[7]
|
|
set_location_assignment PIN_N20 -to gpio_bd_o[8] ; ## led_red[0]
|
|
set_location_assignment PIN_C15 -to gpio_bd_o[9] ; ## led_red[1]
|
|
set_location_assignment PIN_AL28 -to gpio_bd_o[10] ; ## led_red[2]
|
|
set_location_assignment PIN_F11 -to gpio_bd_o[11] ; ## led_red[3]
|
|
set_location_assignment PIN_AJ31 -to gpio_bd_o[12] ; ## led_red[4]
|
|
set_location_assignment PIN_AN34 -to gpio_bd_o[13] ; ## led_red[5]
|
|
set_location_assignment PIN_AJ34 -to gpio_bd_o[14] ; ## led_red[6]
|
|
set_location_assignment PIN_AK33 -to gpio_bd_o[15] ; ## led_red[7]
|
|
set_location_assignment PIN_C8 -to gpio_bd_i[0] ; ## dip_switches[0]
|
|
set_location_assignment PIN_D8 -to gpio_bd_i[1] ; ## dip_switches[1]
|
|
set_location_assignment PIN_E7 -to gpio_bd_i[2] ; ## dip_switches[2]
|
|
set_location_assignment PIN_E6 -to gpio_bd_i[3] ; ## dip_switches[3]
|
|
set_location_assignment PIN_G8 -to gpio_bd_i[4] ; ## dip_switches[4]
|
|
set_location_assignment PIN_F8 -to gpio_bd_i[5] ; ## dip_switches[5]
|
|
set_location_assignment PIN_D15 -to gpio_bd_i[6] ; ## dip_switches[6]
|
|
set_location_assignment PIN_G11 -to gpio_bd_i[7] ; ## dip_switches[7]
|
|
set_location_assignment PIN_D6 -to gpio_bd_i[8] ; ## push_buttons[0]
|
|
set_location_assignment PIN_C6 -to gpio_bd_i[9] ; ## push_buttons[1]
|
|
set_location_assignment PIN_K7 -to gpio_bd_i[10] ; ## push_buttons[2]
|
|
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[0]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[1]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[2]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[3]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[4]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[5]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[6]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[7]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[8]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[9]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[10]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[11]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[12]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[13]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[14]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_o[15]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[0]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[1]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[2]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[3]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[4]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[5]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[6]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[7]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[8]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[9]
|
|
set_instance_assignment -name IO_STANDARD "2.5 V" -to gpio_bd_i[10]
|
|
|
|
set_instance_assignment -name OPTIMIZATION_TECHNIQUE SPEED -to *
|
|
set_instance_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON -to *
|
|
|
|
set_location_assignment FF_X25_Y136_N31 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucke_qr_to_hr|dataout_r[0][0]
|
|
set_location_assignment FF_X25_Y136_N1 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucke_qr_to_hr|dataout_r[0][1]
|
|
set_location_assignment FF_X15_Y136_N56 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucs_n_qr_to_hr|dataout_r[0][0]
|
|
set_location_assignment FF_X15_Y136_N2 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucs_n_qr_to_hr|dataout_r[0][1]
|
|
set_location_assignment FF_X18_Y136_N5 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][0]
|
|
set_location_assignment FF_X18_Y136_N14 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][1]
|
|
set_location_assignment FF_X18_Y136_N35 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][2]
|
|
set_location_assignment FF_X18_Y136_N56 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][3]
|
|
set_location_assignment FF_X18_Y136_N38 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][4]
|
|
set_location_assignment FF_X18_Y136_N29 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ubank_qr_to_hr|dataout_r[0][5]
|
|
set_location_assignment FF_X25_Y136_N14 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][0]
|
|
set_location_assignment FF_X25_Y136_N17 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][1]
|
|
set_location_assignment FF_X25_Y136_N50 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][2]
|
|
set_location_assignment FF_X25_Y136_N44 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][3]
|
|
set_location_assignment FF_X21_Y136_N31 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][4]
|
|
set_location_assignment FF_X21_Y136_N55 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][5]
|
|
set_location_assignment FF_X21_Y136_N43 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][6]
|
|
set_location_assignment FF_X21_Y136_N16 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][7]
|
|
set_location_assignment FF_X20_Y136_N13 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][8]
|
|
set_location_assignment FF_X20_Y136_N37 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][9]
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set_location_assignment FF_X20_Y136_N43 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][10]
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set_location_assignment FF_X20_Y136_N55 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][11]
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set_location_assignment FF_X18_Y136_N22 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][12]
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set_location_assignment FF_X25_Y136_N41 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][13]
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set_location_assignment FF_X25_Y136_N38 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][14]
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set_location_assignment FF_X25_Y136_N35 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][15]
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set_location_assignment FF_X25_Y136_N8 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][16]
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set_location_assignment FF_X21_Y136_N58 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][17]
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set_location_assignment FF_X21_Y136_N40 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][18]
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set_location_assignment FF_X21_Y136_N7 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][19]
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set_location_assignment FF_X21_Y136_N49 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][20]
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set_location_assignment FF_X20_Y136_N7 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][21]
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set_location_assignment FF_X20_Y136_N49 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][22]
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set_location_assignment FF_X20_Y136_N25 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][23]
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set_location_assignment FF_X20_Y136_N31 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][24]
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set_location_assignment FF_X18_Y136_N49 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uaddress_qr_to_hr|dataout_r[0][25]
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set_location_assignment FF_X28_Y136_N47 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ureset_n_qr_to_hr|dataout_r[0][0]
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set_location_assignment FF_X28_Y136_N26 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ureset_n_qr_to_hr|dataout_r[0][1]
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set_location_assignment FF_X18_Y136_N47 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uras_n_qr_to_hr|dataout_r[0][0]
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set_location_assignment FF_X18_Y136_N8 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uras_n_qr_to_hr|dataout_r[0][1]
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set_location_assignment FF_X15_Y136_N7 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucas_n_qr_to_hr|dataout_r[0][0]
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set_location_assignment FF_X15_Y136_N34 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:ucas_n_qr_to_hr|dataout_r[0][1]
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set_location_assignment FF_X15_Y136_N52 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uwe_n_qr_to_hr|dataout_r[0][0]
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set_location_assignment FF_X15_Y136_N40 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uwe_n_qr_to_hr|dataout_r[0][1]
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set_location_assignment FF_X15_Y136_N13 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uodt_qr_to_hr|dataout_r[0][0]
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set_location_assignment FF_X15_Y136_N43 -to system_bd:i_system_bd|system_bd_sys_ddr3_cntrl:sys_ddr3_cntrl|system_bd_sys_ddr3_cntrl_p0:p0|system_bd_sys_ddr3_cntrl_p0_memphy:umemphy|system_bd_sys_ddr3_cntrl_p0_new_io_pads:uio_pads|system_bd_sys_ddr3_cntrl_p0_addr_cmd_pads:uaddr_cmd_pads|system_bd_sys_ddr3_cntrl_p0_simple_ddio_out:uodt_qr_to_hr|dataout_r[0][1]
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# source defaults
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source $ad_hdl_dir/projects/common/altera/sys_gen.tcl
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