332 lines
9.2 KiB
Verilog
332 lines
9.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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DDR_addr,
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DDR_ba,
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DDR_cas_n,
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DDR_ck_n,
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DDR_ck_p,
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DDR_cke,
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DDR_cs_n,
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DDR_dm,
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DDR_dq,
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DDR_dqs_n,
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DDR_dqs_p,
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DDR_odt,
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DDR_ras_n,
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DDR_reset_n,
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DDR_we_n,
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FIXED_IO_ddr_vrn,
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FIXED_IO_ddr_vrp,
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FIXED_IO_mio,
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FIXED_IO_ps_clk,
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FIXED_IO_ps_porb,
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FIXED_IO_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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i2s_mclk,
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i2s_bclk,
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i2s_lrclk,
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i2s_sdata_out,
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i2s_sdata_in,
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spdif,
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iic_scl,
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iic_sda,
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iic_mux_scl,
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iic_mux_sda,
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otg_vbusoc,
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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gpio_txnrx,
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gpio_enable,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status,
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spi_csn,
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spi_clk,
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spi_mosi,
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spi_miso,
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spi_udc_csn_tx,
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spi_udc_csn_rx,
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spi_udc_sclk,
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spi_udc_data);
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inout [14:0] DDR_addr;
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inout [ 2:0] DDR_ba;
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inout DDR_cas_n;
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inout DDR_ck_n;
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inout DDR_ck_p;
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inout DDR_cke;
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inout DDR_cs_n;
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inout [ 3:0] DDR_dm;
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inout [31:0] DDR_dq;
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inout [ 3:0] DDR_dqs_n;
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inout [ 3:0] DDR_dqs_p;
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inout DDR_odt;
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inout DDR_ras_n;
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inout DDR_reset_n;
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inout DDR_we_n;
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inout FIXED_IO_ddr_vrn;
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inout FIXED_IO_ddr_vrp;
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inout [53:0] FIXED_IO_mio;
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inout FIXED_IO_ps_clk;
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inout FIXED_IO_ps_porb;
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inout FIXED_IO_ps_srstb;
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inout [31:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [15:0] hdmi_data;
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output spdif;
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output i2s_mclk;
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output i2s_bclk;
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output i2s_lrclk;
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output i2s_sdata_out;
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input i2s_sdata_in;
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inout iic_scl;
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inout iic_sda;
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inout [ 1:0] iic_mux_scl;
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inout [ 1:0] iic_mux_sda;
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input otg_vbusoc;
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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inout gpio_txnrx;
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inout gpio_enable;
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inout gpio_resetb;
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inout gpio_sync;
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inout gpio_en_agc;
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inout [ 3:0] gpio_ctl;
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inout [ 7:0] gpio_status;
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output spi_csn;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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output spi_udc_csn_tx;
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output spi_udc_csn_rx;
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output spi_udc_sclk;
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output spi_udc_data;
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// internal signals
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wire [48:0] gpio_i;
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wire [48:0] gpio_o;
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wire [48:0] gpio_t;
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wire [ 1:0] iic_mux_scl_i_s;
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wire [ 1:0] iic_mux_scl_o_s;
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wire iic_mux_scl_t_s;
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wire [ 1:0] iic_mux_sda_i_s;
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wire [ 1:0] iic_mux_sda_o_s;
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wire iic_mux_sda_t_s;
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wire [15:0] ps_intrs;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(49)) i_iobuf_gpio (
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.dt ({gpio_t[48:0]}),
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.di ({gpio_o[48:0]}),
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.do ({gpio_i[48:0]}),
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.dio({ gpio_txnrx,
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gpio_enable,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status,
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gpio_bd}));
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ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl (
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.dt ({iic_mux_scl_t_s,iic_mux_scl_t_s}),
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.di (iic_mux_scl_o_s),
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.do (iic_mux_scl_i_s),
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.dio(iic_mux_scl));
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ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_sda (
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.dt ({iic_mux_sda_t_s,iic_mux_sda_t_s}),
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.di (iic_mux_sda_o_s),
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.do (iic_mux_sda_i_s),
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.dio(iic_mux_sda));
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system_wrapper i_system_wrapper (
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.DDR_addr (DDR_addr),
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.DDR_ba (DDR_ba),
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.DDR_cas_n (DDR_cas_n),
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.DDR_ck_n (DDR_ck_n),
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.DDR_ck_p (DDR_ck_p),
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.DDR_cke (DDR_cke),
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.DDR_cs_n (DDR_cs_n),
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.DDR_dm (DDR_dm),
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.DDR_dq (DDR_dq),
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.DDR_dqs_n (DDR_dqs_n),
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.DDR_dqs_p (DDR_dqs_p),
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.DDR_odt (DDR_odt),
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.DDR_ras_n (DDR_ras_n),
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.DDR_reset_n (DDR_reset_n),
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.DDR_we_n (DDR_we_n),
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.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
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.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
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.FIXED_IO_mio (FIXED_IO_mio),
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.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
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.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
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.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
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.GPIO_I (gpio_i),
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.GPIO_O (gpio_o),
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.GPIO_T (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.i2s_bclk (i2s_bclk),
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.i2s_lrclk (i2s_lrclk),
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.i2s_mclk (i2s_mclk),
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.i2s_sdata_in (i2s_sdata_in),
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.i2s_sdata_out (i2s_sdata_out),
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.iic_fmc_scl_io (iic_scl),
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.iic_fmc_sda_io (iic_sda),
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.iic_mux_scl_I (iic_mux_scl_i_s),
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.iic_mux_scl_O (iic_mux_scl_o_s),
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.iic_mux_scl_T (iic_mux_scl_t_s),
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.iic_mux_sda_I (iic_mux_sda_i_s),
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.iic_mux_sda_O (iic_mux_sda_o_s),
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.iic_mux_sda_T (iic_mux_sda_t_s),
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.ps_intr_0 (ps_intrs[0]),
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.ps_intr_1 (ps_intrs[1]),
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.ps_intr_10 (ps_intrs[10]),
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.ps_intr_11 (ps_intrs[11]),
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.ps_intr_12 (ps_intrs[12]),
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.ps_intr_13 (ps_intrs[13]),
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.ps_intr_2 (ps_intrs[2]),
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.ps_intr_3 (ps_intrs[3]),
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.ps_intr_4 (ps_intrs[4]),
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.ps_intr_5 (ps_intrs[5]),
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.ps_intr_6 (ps_intrs[6]),
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.ps_intr_7 (ps_intrs[7]),
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.ps_intr_8 (ps_intrs[8]),
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.ps_intr_9 (ps_intrs[9]),
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.ad9361_dac_dma_irq (ps_intrs[12]),
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.ad9361_adc_dma_irq (ps_intrs[13]),
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.iic_fmc_intr(ps_intrs[11]),
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.otg_vbusoc (otg_vbusoc),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_clk_in_p (rx_clk_in_p),
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.rx_data_in_n (rx_data_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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.spdif (spdif),
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.spi_csn_i (1'b1),
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.spi_csn_o (spi_csn),
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.spi_miso_i (spi_miso),
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.spi_mosi_i (1'b0),
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.spi_mosi_o (spi_mosi),
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.spi_sclk_i (1'b0),
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.spi_sclk_o (spi_clk),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_data_out_n (tx_data_out_n),
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.tx_data_out_p (tx_data_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.spi_udc_clk_i (1'b0),
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.spi_udc_clk_o (spi_udc_sclk),
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.spi_udc_csn_i (1'b1),
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.spi_udc_csn_tx_o (spi_udc_csn_tx),
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.spi_udc_csn_rx_o (spi_udc_csn_rx),
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.spi_udc_mosi_i (spi_udc_data),
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.spi_udc_mosi_o (spi_udc_data),
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.spi_udc_miso_i (1'b0));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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