152 lines
5.5 KiB
VHDL
152 lines
5.5 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2013(c) Analog Devices, Inc.
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-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
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--
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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-- - Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- - Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in
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-- the documentation and/or other materials provided with the
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-- distribution.
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-- - Neither the name of Analog Devices, Inc. nor the names of its
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-- contributors may be used to endorse or promote products derived
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-- from this software without specific prior written permission.
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-- - The use of this software may or may not infringe the patent rights
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-- of one or more patent holders. This license does not release you
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-- from the requirement that you obtain separate licenses from these
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-- patent holders to use this software.
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-- - Use of the software either in source or binary form, must be run
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-- on or directly connected to an Analog Devices Inc. component.
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--
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-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED.
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--
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-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity axi_ctrlif is
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generic
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(
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C_NUM_REG : integer := 32;
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C_S_AXI_DATA_WIDTH : integer := 32;
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C_S_AXI_ADDR_WIDTH : integer := 32;
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C_FAMILY : string := "virtex6"
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);
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port
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(
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-- AXI bus interface
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S_AXI_ACLK : in std_logic;
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S_AXI_ARESETN : in std_logic;
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S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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S_AXI_AWVALID : in std_logic;
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S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
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S_AXI_WVALID : in std_logic;
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S_AXI_BREADY : in std_logic;
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S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
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S_AXI_ARVALID : in std_logic;
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S_AXI_RREADY : in std_logic;
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S_AXI_ARREADY : out std_logic;
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S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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S_AXI_RRESP : out std_logic_vector(1 downto 0);
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S_AXI_RVALID : out std_logic;
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S_AXI_WREADY : out std_logic;
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S_AXI_BRESP : out std_logic_vector(1 downto 0);
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S_AXI_BVALID : out std_logic;
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S_AXI_AWREADY : out std_logic;
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rd_addr : out integer range 0 to C_NUM_REG - 1;
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rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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rd_ack : out std_logic;
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rd_stb : in std_logic;
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wr_addr : out integer range 0 to C_NUM_REG - 1;
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wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
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wr_ack : in std_logic;
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wr_stb : out std_logic
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);
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end entity axi_ctrlif;
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architecture Behavioral of axi_ctrlif is
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type state_type is (IDLE, RESP, ACK);
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signal rd_state : state_type;
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signal wr_state : state_type;
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begin
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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rd_state <= IDLE;
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else
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case rd_state is
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when IDLE =>
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if S_AXI_ARVALID = '1' then
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rd_state <= RESP;
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rd_addr <= to_integer(unsigned(S_AXI_ARADDR((C_S_AXI_ADDR_WIDTH-1) downto 2)));
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end if;
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when RESP =>
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if rd_stb = '1' and S_AXI_RREADY = '1' then
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rd_state <= IDLE;
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end if;
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when others => null;
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end case;
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end if;
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end if;
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end process;
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S_AXI_ARREADY <= '1' when rd_state = IDLE else '0';
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S_AXI_RVALID <= '1' when rd_state = RESP and rd_stb = '1' else '0';
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S_AXI_RRESP <= "00";
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rd_ack <= '1' when rd_state = RESP and S_AXI_RREADY = '1' else '0';
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S_AXI_RDATA <= rd_data;
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process (S_AXI_ACLK)
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begin
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if rising_edge(S_AXI_ACLK) then
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if S_AXI_ARESETN = '0' then
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wr_state <= IDLE;
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else
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case wr_state is
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when IDLE =>
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if S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_ack = '1' then
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wr_state <= ACK;
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end if;
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when ACK =>
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wr_state <= RESP;
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when RESP =>
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if S_AXI_BREADY = '1' then
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wr_state <= IDLE;
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end if;
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end case;
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end if;
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end if;
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end process;
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wr_stb <= '1' when S_AXI_AWVALID = '1' and S_AXI_WVALID = '1' and wr_state = IDLE else '0';
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wr_data <= S_AXI_WDATA;
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wr_addr <= to_integer(unsigned(S_AXI_AWADDR((C_S_AXI_ADDR_WIDTH-1) downto 2)));
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S_AXI_AWREADY <= '1' when wr_state = ACK else '0';
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S_AXI_WREADY <= '1' when wr_state = ACK else '0';
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S_AXI_BRESP <= "00";
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S_AXI_BVALID <= '1' when wr_state = RESP else '0';
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end;
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