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pluto_hdl_adi/library/axi_dmac
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Laszlo Nagy 572089657a axi_dmac: infer interrupt line for Xilinx projects 
The interrupt controller from Microblaze based projects requires that
all its inputs have attributes which define the sensitivity of the
interrupt line. Other case it defaults to EDGE_RISING which is not the
case for DMAC, leading to incorrect interrupt reporting and handling in
case of such projects.
 		2019-04-25 08:25:02 +03:00
..
bd axi_dmac: patch version checking 2018-12-20 10:32:48 +02:00
tb axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
2d_transfer.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
Makefile Makefile: update makefiles 2018-12-21 17:32:48 +02:00
address_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
axi_dmac_burst_memory.v sync_bits: Change I/O names of wires "in" and "out" for VHDL users 2019-04-23 18:03:23 +03:00
axi_dmac_constr.sdc axi_dmac: preparation work for reporting length of partial transfers 2018-09-07 11:38:04 +03:00
axi_dmac_constr.ttcl axi_dmac: early abort support 2018-09-07 11:38:04 +03:00
axi_dmac_hw.tcl axi_dmac: burst_memory: Add support for using asymmetric memory 2018-11-30 23:41:49 +02:00
axi_dmac_ip.tcl axi_dmac: infer interrupt line for Xilinx projects 2019-04-25 08:25:02 +03:00
axi_dmac_pkg_sv.ttcl axi_dmac: ttcl file support for simulation 2018-07-11 11:30:22 +03:00
axi_dmac_regmap.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_regmap_request.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac_reset_manager.v sync_bits: Change I/O names of wires "in" and "out" for VHDL users 2019-04-23 18:03:23 +03:00
axi_dmac_resize_dest.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
axi_dmac_resize_src.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
axi_dmac_response_manager.v axi_dmac: burst_memory: Reset beat counter at the end of each burst 2018-11-30 23:41:49 +02:00
axi_dmac_transfer.v axi_dmac: burst_memory: Add support for using asymmetric memory 2018-11-30 23:41:49 +02:00
axi_register_slice.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
data_mover.v Revert "axi_dmac: assert xfer_request only when ready" 2019-04-18 16:15:55 +03:00
dest_axi_mm.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
dest_axi_stream.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
dest_fifo_inf.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
inc_id.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_arb.v sync_bits: Change I/O names of wires "in" and "out" for VHDL users 2019-04-23 18:03:23 +03:00
request_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
resp.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
response_handler.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
splitter.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_axi_mm.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
src_axi_stream.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_fifo_inf.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00