7a53b99b8b
Currently the DAC FIFO size for the ZC706 DAQ2 project is 16kB. This is quite a limiting size for practical applications. Increase the size to 1MB to allow loading larger waveforms. In this configuration the DAC FIFO will use half of the available BRAM cells in the FPGA. This still leaves quite a few BRAMs available for user application logic added to the design. If a user design should run out of BRAMs nevertheless they can reduce the FIFO size, if not required by the application, to free up some cells. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
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