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Istvan Csomortani 7960b00684 block_design: Update with new clock net variables 
Using the new clock net variables in all Xilinx block designs.
 		2019-06-11 18:13:06 +03:00
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common block_design: Update with new clock net variables 2019-06-11 18:13:06 +03:00
zc706 fmcomms11/zc706: Relax core clock timing to 250MHz/125MHz 2019-06-10 11:23:41 +03:00
Makefile fmcomms11: Initial commit 2019-05-16 13:26:58 +03:00